Lukusa D. Kabulepa

Design of a reconfigurable AES encryption/decryption engine for mobile terminals

This work presents the hardware design of a reconfigurable encryption/decryption engine for the Advanced Encryption Standard (AES) supporting all key lengths. The reconfigurable crypto-engine is integrated as a function unit in a 32 bit RISC processor and can operate in parallel with the standard ALU. Neither the pipeline structure nor the control logic for register forwarding and hazard detection are affected, allowing an easy integration into different RISC architectures. Reconfiguration can be done during runtime, allowing the processor to utilize the arithmetic components and memory elements of the crypto-unit for additional tasks like multiplication in the Galois Field GF(2/sup 8/) required for Reed-Solomon code generation. The RISC processor with the crypto-engine was synthesized using a 0.25 /spl mu/m CMOS technology.

Moment-Based Power Estimation in Very Deep Submicron Technologies

The significant power optimization possibilities in the early stagesof the design flow advice the use of energy evaluation techniquesat high levels of abstraction. With this aim, the present work addressesthe estimation of the energy consumption in very deep submicrontechnologies. Using the characterization of the probabilitydensity function with a projection in an orthogonal polynomialbase, and a symbolic propagation mechanism, a technique is presentedto estimate the dynamic and static power consumption indigital systems. The proposed approach has been validated withcircuits and excitations from realistic applications. Comparisonswith reference transistor and bit level simulations are reported inorder to asses the the accuracy of the technique.

Exploring the Capabilities of Reconfigurable Hardware for OFDM-Based Wlans

In this paper, the potential of reconfigurable hardware in wireless communication systems is evaluated. As most of the published works aim at the usage of reconfigurable architectures as a universal platform for different standards, the optimization capabilities of reconfiguration techniques for hardware modules within one standard are often not considered. This work focuses on the hardware optimization within one transmission scheme, namely OFDM (Orthogonal Frequency Division Multiplexing). By making use of special characteristics of packet-based WLANs and standard specifications, functional blocks of an OFDM receiver can be mapped on the same hardware. Even performance enhancements can be achieved without any additional hardware.

On the rapid prototyping of equalizers for OFDM systems

This article discusses hardware-oriented issues related to the compensation of channel distortions in packed-based mobile Orthogonal Frequency Division Multiplexing (OFDM) systems. The adopted evaluation approach relies upon Field-Programmable Gate Array (FPGA) prototyping. Depending on radio channel parameters and the modulation scheme, the required computation effort for the compensation of channel distortions can depict significant variations. In order to perform a trade-off analysis between complexity and performance, different compensation methods for channel distortions have been simulated within an OFDM simulation chain. Based on these results, hardware models have been created and prototyped onto a FPGA. The performance of the models with regard to the hardware efficiency is evaluated by integrating the prototyped components into the OFDM simulation chain. The hardware designs and simulations have been done according to the high-speed wireless LAN standard HiperLAN/2.

Design of an efficient OFDM burst synchronization scheme

The realization of a frame synchronization scheme represents a critical task in the design process of an OFDM receiver. A loss of orthogonality between the multiplexed subcarriers can result in severe bit error rate degradations. In this paper we compare different OFDM burst synchronization schemes in terms of hardware relevant aspects such as chip area/costs and impact of quantization effects. Furthermore we propose an efficient synchronization algorithm for OFDM burst applications. Simulation results related to a HiperLAN/2 model are provided.

Estimation of Power Consumption in Encoded Data Buses

Because of the increasing importance of cross coupled capacitances in deep submicron technologies, it is of great interest to extend the existing high-level power estimation techniques by considering the spatial correlation between adjacent lines. This work addresses the modeling and estimation of power dissipation in on-chip buses based on the statistical properties of data sequences. Using the derived models, a power estimation technique is proposed and evaluated for various coding schemes. For different DSP applications, our results depict less than 5% discrepancy with precise bit level estimations.

Reconfiguration requirements for high speed wireless communication systems

This paper focuses on the reconfiguration requirements of hardware platforms for high speed wireless communication systems. Due to the underlying trade-off between flexibility and efficiency, many reconfigurable hardware solutions and FPGA implementations are prone to significant energy and performance penalties in comparison to application specific hardware designs. These penalties can only be alleviated by designing reconfigurable architectures for selected applications fields, since each application field has only a limited set of flexibility requirements. In this paper the analysis is conducted for emerging wireless communication standards based on the OFDM (Orthogonal Frequency Division Multiplexing) or CDMA (Code Division Multiple Access) transmission technique. The requirements for the physical and the medium access layers are analyzed separately. Focus is also set on different market segments.

Efficient estimation of signal transition activity in MAC architectures

Because of the increasing demand of portable digital systems, it is of great interest to extend the existing high-level power estimation techniques to handle architectures with non linear components, as they appear in relevant practical applications. In this paper we focus on the estimation of the transition activity in MAC structures implementing FIR filters. Based on a divide and conquer approach, an accurate yet efficient estimation procedure is developed. The technique has been evaluated for different synthetic and real data sets. In all cases, our results depict only very slight discrepancies with respect to precise bit level simulations.

Analysis of bandpass sigma-delta modulator architectures

This work analyses two architectures of bandpass sigma delta modulators, in order to find their sensitivity against operational amplifier finite voltage gain, having in mind a switched capacitor realization of both architectures. Expressions for the ideal signal to noise ratio and dynamic range of both architectures are found, as well as a model of the degradation of the mentioned parameters due to finite values of the voltage gain. The proposed model is then compared with nonlinear high level simulations including the effect of finite voltage gain.

Transition activity estimation for generic data distributions [power estimation]

Due to the increasing demand of portable digital systems, it is of great interest to extend the existing high-level power estimation techniques to handle flexible non-Gaussian data models, as they appear in relevant applications such as signal correlators or OFDM synchronization units. This work addresses the modeling and estimation of signal activity in random signals based on their statistical properties. Using the derived models, an estimation technique is proposed and evaluated for practical circuits. Bit level simulation results show the excellent accuracy of the proposed approach.