A. Garcia Ortiz

Inserting Data Encoding Techniques into NoC-Based Systems

This work investigates the reduction of power consumption in networks-on-chip through the reduction of transition activity using data coding schemes. Power macromodels for NoC and encoding modules were built, allowing the estimation of the power consumption as a function of the transition activity at each module input. Power macromodels are embedded in a system model and a set of simulations are performed, analyzing the trade-off between the power savings due to coding schemes versus the power consumption overhead due to the encoding and decoding modules

Partial bus-invert bus encoding schemes for low-power DSP systems considering inter-wire capacitance

In this work, we develop simple yet very effective bus encoding schemes that dramatically reduce both self and coupling transition activity in common DSP signals. We show that, efficient low-power codes must cope with the different statistical characteristics of the most and least significant bits. On one hand, the high correlation in the most significant bits can be exploited by employing a simple non-redundant code. On the other hand, Bus Invert based codes are very efficient when applied only on the poorly correlated uniformly distributed least significant bits. The latter should not be employed on the most significant bits in order to preserve their high correlation. Additionally, we show that low-power codes can be easily compared by means of a simple graphical method.

Design of an efficient OFDM burst synchronization scheme

The realization of a frame synchronization scheme represents a critical task in the design process of an OFDM receiver. A loss of orthogonality between the multiplexed subcarriers can result in severe bit error rate degradations. In this paper we compare different OFDM burst synchronization schemes in terms of hardware relevant aspects such as chip area/costs and impact of quantization effects. Furthermore we propose an efficient synchronization algorithm for OFDM burst applications. Simulation results related to a HiperLAN/2 model are provided.

On the necessity of combining coding with spacing and shielding for improving performance and power in very deep sub-micron interconnects

In this work, the necessity of combining signal encoding schemes with low-level anti-crosstalk techniques like spacing and shielding is analyzed. It is shown that in order to increase the throughput improvement and/or reduce the power consumption, coding schemes should be integrated with layout techniques since methods like spacing and shielding can be regarded as very simple encoding schemes. On this basis, a theoretical framework for assessing the improvement in throughput and/or power consumption is constructed. Furthermore, several possibilities to integrate coding with classical anti-crosstalk techniques are discussed.

On timing and power consumption in inductively coupled on-chip interconnects

This work analyses the effects on timing and power consumption of the inductive coupling in long high-frequency on-chip interconnects. By means of extensive simulations it is shown that the common assumptions used until now when considering only line inductance effects do not hold. In fact, signal integrity, voltage glitches and cross-talk, signal delay, rise and fall times, as well as power dissipation strongly depend on the mutual inductances and the input data toggling pattern.

A stochastic framework for communication architecture evaluation in networks-on-chip

With technology improvements, the main bottleneck in single chip systems in terms of performance, power consumption, and design reuse is proving to be generated by the on-chip communication architecture. Therefore, packet oriented on-chip interconnection schemes have been proposed as an alternative to traditional bus-based structures, which are inherently non scalable. However, such interconnection architectures have to be during the very early stages of the design flow. The objective of this work is to present an application independent stochastic framework for high level performance analysis of networks-on-chip based communication architectures. Such a template allows the designer the performance evaluation of various competing on-chip communication architectures early in the design flow.

Transition activity estimation for generic data distributions [power estimation]

Due to the increasing demand of portable digital systems, it is of great interest to extend the existing high-level power estimation techniques to handle flexible non-Gaussian data models, as they appear in relevant applications such as signal correlators or OFDM synchronization units. This work addresses the modeling and estimation of signal activity in random signals based on their statistical properties. Using the derived models, an estimation technique is proposed and evaluated for practical circuits. Bit level simulation results show the excellent accuracy of the proposed approach.

Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures

With technology improvements, the main bottleneck in terms of performance, power consumption, and design reuse in single chip systems is proving to be generated by the on-chip communication architecture. Benefiting from the non-uniformity of the workload in various signal processing applications, several dynamic power management policies can be envisaged. Nevertheless, the integration of on-line power, performance and information-flow management strategies based on traffic monitoring in (dynamically) reconfigurable templates has yet to be explicitly tackled. The main objective of this work is to define the concept of run-time functional optimization of application specific standard products, and show the importance of integrating such techniques in reconfigurable platforms and especially their communication architectures.

Hardware-Assisted Signal Activity Analysis for Power Estimation in Rapid Prototyped Systems

In this paper, a technique is proposed to gather statistical data concerning the activity of the internal signals in a complex application. By using an architecture precise rapid prototyping system, the signals can be analyzed over a long period of time and therefore, a realistic estimation of the signal characteristics is obtained. This information can be used for estimating the power consumption in the final system as well as for a later refinement of the communication structures and processing blocks. In order to account for deep submicron effects, not only transition activity but also inter-wire correlations are considered. Because of the huge amount of data that would be generated by a real-time monitoring, a statistical hardware compression module was implemented for embedding it into prototyped designs. It allows the trade off between hardware efficiency and estimation accuracy, in order to offer a flexible usage of the prototyping resources. The proposed approach has been validated in a baseband implementation and prototype of a simplified OFDM transmitter.

Power reduction techniques for an OFDM burst synchronization core

The design of the synchronization circuitry constitutes a challenging task in the implementation of a OFDM modem for packet-oriented applications. This paper discusses the suitability and efficiency of low power techniques for the design of a burst-mode OFDM synchronization unit. The architecture and system-level simulations refer to the parameters defined for a HiperLAN/2 environment model. The target technology for the VLSI hardware realization is a standard 0.35 /spl mu/m CMOS process.