Lunyu Ma

J-Springs - innovative compliant interconnects for next-generation packaging

The advances made in the design and the fabrication of integrated circuits (ICs) have far outpaced the advances made in the design and the fabrication of chip-to-substrate interconnects as well as high-density substrates. According to the International Technology Roadmap for Semiconductors (ITRS) for 2014, the chip-to-substrate interconnects should have a pitch of about 40 /spl mu/m and should be able to accommodate the coefficient of thermal expansion (CTE) mismatch of low-cost organic substrates without resorting to expensive reliability solutions. In this paper, a novel chip-to-substrate interconnect - J-Spring - is proposed and fabricated. J-Spring is a compliant interconnect fabricated through stress-engineered metal layers, and the fabrication is based on traditional IC fabrication process. The J-Springs have excellent compliance in the three orthogonal directions, and the interconnect is designed to accommodate the high differential displacement due to CTE mismatch between silicon ICs and organic substrates under various thermal conditions.

/spl beta/-Helix: a lithography-based compliant off-chip interconnect

Microsystems packages continue to demand lower cost, higher reliability, better performance and smaller size. Compliant wafer-level interconnects show great potential for next-generation packaging. The proposed /spl beta/-Helix interconnect, an electroplated compliant wafer-level off-chip interconnect, can facilitate wafer-level probing as well as wafer-level packaging without the need for an underfill. The fabrication of the /spl beta/-Helix interconnect is similar to conventional integrated circuit (IC) fabrication processes and is based on electroplating and photolithography. /spl beta/-Helix interconnect has good mechanical compliance in the three orthogonal directions and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate. In this paper, we report the wafer-level fabrication of area-arrayed /spl beta/-Helix interconnects. The geometry effect on the mechanical compliance and the electrical parasitics of /spl beta/-Helix interconnect has been studied. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is also found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed. Using response surface methodology (RSM), an optimization has been done, and the optimal compliant /spl beta/-Helix interconnect will have a total standoff height of 110 /spl mu/m, radius of 37 /spl mu/m and cross section area of 525 /spl mu/m/sup 2/. It is also found that the structure self-weight effect during the fabrication and the die and heat sink weights during the assembly have negligible effect on the /spl beta/-Helix interconnect, especially when the interconnect density is high.

Design optimization of one-turn helix: a novel compliant off-chip interconnect

As the rapid advances in integrated circuit (IC) design and fabrication continue to challenge and push the electronic packaging technology, in terms of fine pitch, high performance, low cost, and good reliability, compliant interconnects show great potential for next-generation packaging. One-turn helix (OTH) interconnect, a compliant chip-to-next level substrate or off-chip interconnect, is proposed in this work, and this interconnect can facilitate wafer-level probing as well as wafer-level packaging without the need for an underfill. The interconnect has high mechanical compliance in the three orthogonal directions, and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and an organic substrate. The fabrication of the helix interconnect is similar to the standard IC fabrication, and the wafer-level packaging makes it cost effective. In this paper, we report the fabrication of an area array of helix interconnects on a silicon wafer. Also, we have studied the effect of interconnect geometry parameters on its mechanical compliance and electrical parasitics. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed for the design of OTH interconnect. An optimization technique using response surface methodology has been applied to select the optimal structure parameters. The optimal compliant OTH interconnect will have a total standoff height of about 100 /spl mu/m, a radius of about 35 /spl mu/m and a cross section area of about 430 /spl mu/m/sup 2/.

Compliant cantilevered spring interconnects for flip-chip packaging

A new highly-compliant cantilevered spring interconnect is being developed to enable a fine-pitch, high density I/O architecture for the next generation chip and probing technology. This technology meets the requirements of National Technology Roadmap for Semiconductor (NTRS) for 2012 and beyond. Based on its unique structure, a new contact mode - sliding contact with no solder is being tested. To understand the reliability of the package with this novel compliant spring interconnect structure and the typical behavior of the sliding contact, test vehicles with different orientations of the cantilevered springs (21 /spl mu/m pitch) have been fabricated, assembled and subjected to thermal cycling test. In-situ resistance and temperature measurements have been conducted. Material characterization of underfill has also been conducted.

Design and optimization of a novel compliant off-chip interconnect One-Turn Helix

As the rapid advances in IC design and fabrication continue to challenge and push the electronic packaging technology, in terms of fine pitch, high performance, low cost, and good reliability, compliant interconnects show great advantages for next-generation packaging. A novel compliant off-chip interconnect, One-Turn Helix (OTH), is designed as an underfill-free interconnect. It has excellent compliance in all directions to compensate the coefficient of thermal expansion (CTE) mismatch between the silicon die and an organic substrate. The fabrication of OTH is similar to standard IC fabrication, and wafer-level packaging makes it cost effective. In this work, we study the effect of geometry parameters on mechanical and electrical performance of OTH. Thinner and narrower arcuate beam with larger radius and taller post are found to have better mechanical compliance. However, it is found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed for the design of OTH. Response surface methodology and an optimization technique have been used to select the optimal OTH structure parameters.

Design optimization of One-Turn Helix - a novel compliant off-chip interconnect

As the rapid advances in IC design and fabrication continue to challenge and push the electronic packaging technology, in terms of fine pitch, high performance, low cost, and good reliability, compliant interconnects show great advantages for next-generation packaging. One-Turn Helix (OTH), is designed as a compliant off-chip interconnect that allowing wafer-level probing and packaging without underfill. It has excellent compliance in all directions to compensate the coefficient of thermal expansion (CTE) mismatch between the silicon die and an organic substrate. The fabrication of OTH is similar to standard IC fabrication, and wafer-level packaging makes it cost effective. In this work, we study the effect of geometry parameters on mechanical and electrical performance of OTH. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed for the design of OTH. Response surface methodology and an optimization technique have been used to select the optimal OTH structure parameters.

Design and Development of Stress-Engineered Compliant Interconnect for Microelectronic Packaging

Power and latency are fast becoming major bottlenecks in the design of high performance microprocessors and computers. Power relates to both consumption and dissipation, and therefore, effective power distribution design and thermal management solutions are required. Latency is caused by the global interconnects on the integrated circuit (IC) that span at least half a chip edge due to the resistance–capacitance (RC) and transmission line delay [1]. Limits to chip power dissipation and power density and limits on hyper-pipelining in microprocessors threaten to impede the exponential growth in microprocessor performance. In contrast, multicore processors can continue to provide a historical performance growth on most consumer and business applications provided that the power efficiency of the cores stays within reasonable power budgets. To sustain the dramatic performance growth, a rapid increase in the number of cores per die and a corresponding growth in off-chip bandwidth are required [2]. Thus, it is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors (ITRS) (21.1) that by the year 2018, with the IC node size shrinking to 22 nm by 2016 and 14 nm by 2020, the chip-to-substrate area-array input–output interconnects will require a pitch of 70 μm [3]. Furthermore, to reduce the RC and transmission line delay, low-K dielectric/Cu and ultra-low-K dielectric/Cu interconnects on silicon will become increasingly common. In such ICs, the thermo-mechanical stresses induced by the chip-to-substrate interconnects could crack or delaminate the dielectric material causing reliability problems.

Mechanical and Electrical Study of Linear Spring and J-Spring

The integrated circuit (IC) fabrication technology continues to push the limits of microelectronics packaging technologies. Today millions of transistors can be fabricated in a chip of about 1 cm × 1 cm in size, and the required I/O density is about 1600/cm2 . Although tremendous advances have been made in die to substrate interconnect technologies as well as substrate/PWB technologies, these advances have not kept pace with advances in semiconductor technology, and therefore, continue to be a bottleneck for further advances in semiconductor technologies. In addition to fabrication constraints, low cost and reliability are other requirements that affect interconnect development. Wafer-level Packaging (WLP) is an effective solution to address some of these issues. A compliant interconnect, called “J-Spring”, has been proposed and developed at Georgia Institute of Technology. Although based on the same concept of inherent stress-gradient used in the linear spring, the J-Spring will provide greater in-plane compliance. These compliant interconnects can be fabricated in batch at wafer level and the pitch can be as low as 30 μm. The fine pitch can meet and exceed the requirements of International Technology Roadmap for Semiconductor (ITRS) for 2011 [ITRS, 2001] and beyond. J-Springs with different radius, angle, width, and release length have been fabricated on a test wafer. Numerical model has been created to determine the release height based on J-Spring geometry and stress gradients. Also, the compliance of J-Spring has been determined in three orthogonal directions using parametric numerical models. The compliance of J-Spring is compared with the compliance of the linear spring. The proposed compliant interconnects can accommodate the differential displacement due to CTE mismatch between the die and the substrate. In addition, to their mechanical characteristics, their electrical characteristics have been studied as well. The electrical characteristics are dependent on the geometry, dimensions and the materials used.Copyright

Three-Mask Fabrication and Optimized Design of First-Level Free-Standing Interconnect for Microelectronics Application

Advances in compliant off-chip interconnects have achieved great strides. G-Helix, an electroplated compliant chip-to-substrate interconnect has the potential for accomplishing low-cost, easy-to-fabricate, wafer-level packaging. In this work, the design, fabrication, optimization and reliability of the G-Helix compliant off-chip interconnects have been studied. A three-mask process was used to successfully fabricate the free-standing G-Helix compliant interconnect. The mechanical compliance and the electrical parasitics were studied through numerical and analytical models. Response Surface Methodology (RSM) was used to maximize the mechanical compliance and minimize the electrical parasitics as well as the stresses induced in the interconnect. It is also seen through the models that an array of interconnects will be able to withstand the die and the heat-sink weight without plastically yielding. Also, the G-Helix interconnect assembly on organic printed circuit board using lead-free solder will be able to withstand more than 1000 accelerated thermal cycles without the need for an underfill.Copyright

Novel nanospring interconnects for high-density applications

A new cantilevered structure, called the nanospring, is being developed to enable a fine-pitch, high density I/O architecture for the next generation chip and probing technology. This technology meets the requirements of the National Technology Roadmap for Semiconductors (NTRS) for 2012 and beyond. Based on its unique structure, a new contact mode of sliding contact with no solder is being tested. To understand the reliability of the package with this novel compliant structure and the typical behavior of sliding contacts, test vehicles with different orientations of the nanospring (21 /spl mu/m pitch) have been fabricated, assembled and subjected to thermal cycling tests. In-situ resistance and temperature measurements have been conducted.