Suresh K. Sitaraman

The SOP for miniaturized, mixed-signal computing, communication, and consumer systems of the next decade

From cell phones to biomedical systems, modern life is inexorably dependent on the complex convergence of technologies into stand-alone products designed to provide a complete solution in small, highly integrated systems with computing, communication, biomedical and consumer functions. The concept of system-on-package (SOP) originated in the mid-1990s at the NSF-funded Packaging Research Center at the Georgia Institute of Technology. This can be thought of as a conceptual paradigm in which the package, and not the bulky board, as the system and the package provides all the system functions in one single module, not as an assemblage of discrete components to be connected together, but as a continuous merging of various integrated thin film technologies in a small package. In the SOP concept, this is accomplished by codesign and fabrication of digital, optical, RF and sensor functions in both IC and the package, thus distinguishing between what function is accomplished best at IC level and at package level. In this paradigm, ICs are viewed as being best for transistor density while the package is viewed as being best for RF, optical and certain digital-function integration. The SOP concept is demonstrated for a conceptual broad-band system called an intelligent network communicator (INC). Its testbed acts as both a leading-edge research and teaching platform in which students, faculty, research scientists, and member companies evaluate the validity of SOP technology from design to fabrication to integration, test, cost and reliability. The testbed explores optical bit stream switching up to 100 GHz, digital signals up to 5-20 GHz, decoupling capacitor integration concepts to reduce simultaneous switching noise of power beyond 100 W/chip, design, modeling and fabrication of embedded components for RF, microwave, and millimeter wave applications up to 60 GHz. This article reviews a number of SOP technologies which have been developed and integrated into SOP test bed. These are: 1) convergent SOP-based INC system design and architecture, 2) digital SOP and its fabrication for signal and power integrity, 3) optical SOP fabrication with embedded actives and passives, 4) RF SOP for high Q-embedded inductors, filters and other RF components, 5) mixed signal electrical test, 6) mixed signal reliability, and 7) demonstration of SOP by INC prototype system.

Failure mechanisms and optimum design for electroplated copper Through-Silicon Vias (TSV)

Through-Silicon Vias (TSVs) have garnered a lot of interest in recent years because TSV is a key enabling technology for three dimensional (3D) Integrated Circuit (IC) stacking, silicon interposer technology, and advanced wafer level packaging (WLP). There has been significant effort in TSV fabrication and electrical design. However, considerably less work has been done on thermo-mechanical analysis and mechanical design of these structures. Due to the high coefficient of thermal expansion (CTE) mismatch between Si and the conducting material in the vias, thermo-mechanical reliability is a major concern. This paper uses Finite-Element (FE) models and X-ray diffraction (XRD) experiments for the thermo-mechanical analysis of TSVs. Two-dimensional thermo-mechanical Finite-element models have been built to analyze the stress/strain distribution in the TSV structures, and the models show that large stress gradients and plastic deformation exist near the corner of electroplated Cu pads. The stress results from the finite-element models have been compared against XRD experimental data. A fracture mechanics analysis has also been performed, and the fracture analysis shows that Cu/SiO2 interfacial cracks and SiO2 cohesive cracks are more likely to initiate and propagate at those corner locations.

Magnetic Alignment of Hexagonal Boron Nitride Platelets in Polymer Matrix: Toward High Performance Anisotropic Polymer Composites for Electronic Encapsulation

We report magnetic alignment of hexagonal boron nitride (hBN) platelets and the outstanding material properties of its polymer composite. The magnetically responsive hBN is produced by surface modification of iron oxide, and their orientations can be controlled by applying an external magnetic field during polymer curing. Owing to the anisotropic properties of hBN, the epoxy composite with aligned hBN platelets shows interesting properties along the alignment direction, including significantly reduced coefficient of thermal expansion, reaching ∼28.7 ppm/°C, and enhanced thermal conductivity, 104% higher than that of unaligned counterpart, both of which are observed at a low filler loading of 20 wt %. Our modeling suggests the filler alignment is the major reason for these intriguing material properties. Finite element analysis reveals promising applications for the magnetically aligned hBN-based composites in modern microelectronic packaging.

Elastic–plastic characterization of thin films using nanoindentation technique

Experimental determination of elastic and plastic properties of thin films with a thickness of 1 μm or less continues to be a challenging task. This article presents a methodology that combines the nanoindentation technique and finite element modeling to characterize the mechanical (elastic and plastic) properties of a titanium thin film. The experimental results show that the elastic property (Youngs modulus) of the titanium thin film does not change compared to the bulk titanium. Results also show that the plastic properties (yield stress and strain hardening exponent) of the titanium thin film are higher than those of the bulk titanium. The methodology outlined in this article can also be used to study the mechanical properties of other thin films and small volume materials.

J-Springs - innovative compliant interconnects for next-generation packaging

The advances made in the design and the fabrication of integrated circuits (ICs) have far outpaced the advances made in the design and the fabrication of chip-to-substrate interconnects as well as high-density substrates. According to the International Technology Roadmap for Semiconductors (ITRS) for 2014, the chip-to-substrate interconnects should have a pitch of about 40 /spl mu/m and should be able to accommodate the coefficient of thermal expansion (CTE) mismatch of low-cost organic substrates without resorting to expensive reliability solutions. In this paper, a novel chip-to-substrate interconnect - J-Spring - is proposed and fabricated. J-Spring is a compliant interconnect fabricated through stress-engineered metal layers, and the fabrication is based on traditional IC fabrication process. The J-Springs have excellent compliance in the three orthogonal directions, and the interconnect is designed to accommodate the high differential displacement due to CTE mismatch between silicon ICs and organic substrates under various thermal conditions.

An integrated process modeling methodology and module for sequential multilayered substrate fabrication using a coupled cure-thermal-stress analysis approach

An integrated process modeling methodology using a coupled cure-thermal-stress analysis approach has been developed to determine the evolution of warpage and stresses during the sequential fabrication of high-density electronic packaging structures. The process modeling methodology has been demonstrated, for example, with a bi-layer structure consisting of a 3 mil (76.2 /spl mu/m) thick Vialux 81 photo-definable dry film (PDDF) polymer on a silicon substrate. Extensive material characterization of the thermo-mechanical properties of the thin film polymer is presented, including the development of a viscoelastic material model. The predicted warpage values have been validated with shadow Moire experiments, while the predicted stress values have been validated with experimental data using the Flexus Thin Film Stress Measurement Apparatus. Good agreement is seen between the predicted and the experimental warpage and stress values during the entire cure cycle. Finally, the importance of incorporating viscoelastic polymer behavior and processing history is emphasized in the context of developing the multi-layered high-density wiring integrated substrate fabrication process.

A knowledge-based system for process-sequence design in axisymmetric sheet-metal forming

Abstract A hybrid Computer-Aided Engineering (CAE) system for automatic process-sequence design for the manufacture of axisymmetric sheet-metal components has been developed. The input to the CAE system is the final sheet-metal object geometry that needs to be manufactured, and the output from the system is the process sequence with intermediate object geometries. Two main components of the hybrid CAE system are a knowledge-based expert-system module (symbolic module) and a process-modeling analysis module (numeric module). The knowledge-based system module will first generate an initial-guess process sequence based on experience-based die-design guidelines, and this process sequence will then be tested for defects and failures by mathematically modeling the sheet-metal forming process using the analysis module. The analysis module will formulate mechanics of metal forming and predict stresses and strains in the deformed geometry and punch load versus displacement. This paper describes the knowledge-based system and compares process sequences outputted by the system with corresponding process sequences from industrial practice. It was found through several test cases that the blank diameter and the number of stations suggested by the knowledge-based system compare well with those used in industrial practice.

Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC

In this work, we propose an efficient and accurate full-chip through-silicon-via (TSV) interfacial crack analysis flow and design optimization methodology to alleviate TSV interfacial crack problems in 3D ICs. First, we analyze TSV interfacial crack at TSV/dielectric liner interface caused by TSV-induced thermo-mechanical stress. Then, we explore the impact of TSV placement in conjunction with various associated structures such as landing pad and dielectric liner on TSV interfacial crack. Next, we present a full-chip TSV interfacial crack analysis methodology based on design of experiments (DOE) and response surface method (RSM). Finally, we propose a design optimization methodology to mitigate the mechanical reliability problems in 3D ICs.

Thermo-mechanical analysis of solder joint fatigue and creep in a flip chip on board package subjected to temperature cycling loading

Thermo-mechanical stress analysis was conducted on a flip-chip-on-board (FCOB) package with underfill encapsulation. The solder joint fatigue and creep deformation response were modeled for a typical temperature cycling loading of -55 to 125 C. Two temperature cycling loading models with and without the curing part of the temperature history for the encapsulation process were investigated. Two-dimensional plane-strain finite element models of the FCOB package were employed. Elasto-plastic and creep deformation behavior of solder was simulated under the temperature cycling conditions to obtain the stress and strain results. The finite element strain results were used in fatigue life prediction models.

/spl beta/-Helix: a lithography-based compliant off-chip interconnect

Microsystems packages continue to demand lower cost, higher reliability, better performance and smaller size. Compliant wafer-level interconnects show great potential for next-generation packaging. The proposed /spl beta/-Helix interconnect, an electroplated compliant wafer-level off-chip interconnect, can facilitate wafer-level probing as well as wafer-level packaging without the need for an underfill. The fabrication of the /spl beta/-Helix interconnect is similar to conventional integrated circuit (IC) fabrication processes and is based on electroplating and photolithography. /spl beta/-Helix interconnect has good mechanical compliance in the three orthogonal directions and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate. In this paper, we report the wafer-level fabrication of area-arrayed /spl beta/-Helix interconnects. The geometry effect on the mechanical compliance and the electrical parasitics of /spl beta/-Helix interconnect has been studied. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is also found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed. Using response surface methodology (RSM), an optimization has been done, and the optimal compliant /spl beta/-Helix interconnect will have a total standoff height of 110 /spl mu/m, radius of 37 /spl mu/m and cross section area of 525 /spl mu/m/sup 2/. It is also found that the structure self-weight effect during the fabrication and the die and heat sink weights during the assembly have negligible effect on the /spl beta/-Helix interconnect, especially when the interconnect density is high.