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Dive into the research topics where Lutz Dathe is active.

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Featured researches published by Lutz Dathe.


IEEE Journal of Solid-state Circuits | 2006

A Fully Integrated 2.4-GHz IEEE 802.15.4-Compliant Transceiver for ZigBee™ Applications

Wolfram Kluge; Frank Poegel; Hendrik Roller; Matthias Lange; Tilo Ferchland; Lutz Dathe; Dietmar Eggert

A single-chip 2.4-GHz CMOS radio transceiver with integrated baseband processing according to the IEEE 802.15.4 standard is presented. The transceiver consumes 14.7 mA in receive mode and 15.7 mA in transmit mode. The receiver uses a low-IF topology for high sensitivity and low power consumption, and achieves -101 dBm sensitivity for 1% packet error rate. The transmitter topology is based on a PLL direct-modulation scheme. Optimizations of architecture and circuit design level in order to reduce the transceiver power consumption are described. Special attention is paid to the RF front-end design which consumes 2.4mA in receive mode and features bidirectional RF pins. The 5.77 mm2 chip is implemented in a standard 0.18-mum CMOS technology. The transmitter delivers +3 dBm into the 100-Omega differential antenna port


international solid-state circuits conference | 2006

A Fully Integrated 2.4GHz IEEE 802.15.4 Compliant Transceiver for ZigBee Applications

Wolfram Kluge; Frank Poegel; Hendrik Roller; Matthias Lange; Tilo Ferchland; Lutz Dathe; Dietmar Eggert

A 0.18mum CMOS low-IF transceiver with integrated baseband processing according to IEEE 802.15.4 is described. The 5.77mm2 die draws 14.7mA (RX) and 15.7mA (TX) while achieving -102dBm RX sensitivity and 3dBm TX power. The differential input 2.4mA RX RF-frontend provides 5.7dB system noise figure


international solid-state circuits conference | 2003

A 2.4GHz CMOS transceiver for 802.11b wireless LANs

Wolfram Kluge; Lutz Dathe; Rolf Jaehne; S. Ehrenreich; Dietmer Eggert

A 0.25/spl mu/m CMOS zero-IF transceiver with VCO and PLL (-111dBc/Hz at 1 MHz) has been implemented. The 3.1/spl times/3.1 mm/sup 2/ IC draws 86mA (RX) and 73mA (TX) from a 2.5V supply. The receiver exhibits a 5dB noise figure and 5/spl mu/s AGC settling time. RX channel filter, TX pulse shaping filter, filter calibration circuitry, 6b ADC, bandgap reference and TX preamplifier are included and controlled by a digital interface.


Archive | 2002

Circuit for tuning an active filter

Lutz Dathe; Henry Drescher


Archive | 2003

Circuit and a method for controlling the bias current in a switched capacitor circuit

Rolf Jaehne; Lutz Dathe; Andreas Huschka


Archive | 2002

Integrated RF signal level detector usable for automatic power level control

Sebastian Ehrenreich; Lutz Dathe; Karl-Heinz Sandig


Archive | 2002

Digital automatic gain control for transceiver devices

Wolfram Kluge; Lutz Dathe; Dietmar Eggert


Archive | 2002

Digital automatic gain controlling in direct-conversion receivers

Wolfram Kluge; Lutz Dathe; Jörg Hönig


Archive | 2002

Phase system rotation for power estimation

Lutz Dathe; Wolfram Kluge; Dietmer Eggert


Archive | 2002

Direct conversion receiver having a gain-setting dependent filter parameter

Wolfram Kluge; Lutz Dathe; Jörg Hönig

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Rolf Jaehne

Advanced Micro Devices

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