Werner Erhard

Optical interconnects for neural and reconfigurable VLSI architectures

The increasing transistor density in very large-scale integrated (VLSI) circuits and the limited pin member in the off-chip communication lead to a situation described as interconnect crisis in micro-electronics. Optoelectronic VLSI (OE-VLSI) circuits using short-distance optical interconnects and optoelectronic devices like microlaser, modulator, and detector arrays for optical off-chip sending and receiving offer a technology to overcome this crisis. However, in order to exploit efficiently the potential of thousands of optical off-chip interconnects, an appropriate VLSI architecture is required. We show for the example of neural and reconfigurable VLSI architectures that fine-grain architectures fulfill these requirements. An OE-VLSI circuit realization based on multiple quantum-well modulators functioning as two-dimensional (2-D) optical input/output (I/O) interface for the chip is presented. Due to the parallel optical interface, and improvement of two to three orders of magnitude in the throughput performance is possible compared to all-electronic solutions. For the optical interconnects, a planar-integrated free-space optical system has been designed leading to an optical multichip module. Such a system has been fabricated and experimentally characterized. Furthermore, we designed an manufactured fiber arrays, which will be the core element for a convenient test station for the 2-D optoelectronic I/O interface of OE-VLSI circuits.

Network traffic analysis and security monitoring with UniMon

This paper introduces an adaptable, flexible and portable network traffic monitor. UniMon (Universal Network Traffic Monitor) is an external and passive network traffic monitor that has been designed in such a way that it can easily be adapted to any type of network and protocols. As a software monitor, UniMon may run on arbitrary workstations within an Ethernet. UniMon aims at offering total network visibility for all the seven ISO/OSI layers and so give a complete analysis of each network packet it captures. UniMon is a suitable tool for network security monitoring and also for network performance monitoring and troubleshooting.

First steps towards a reconfigurable asynchronous system

This paper proposes a system based on Petri nets to implement asynchronous circuits by reconfigurable hardware automatically. The description, simulation, and analysis and synthesis of the structure and behavior of asynchronous systems should be possible at different levels of abstraction. The designed system should also be capable of implementing synchronous circuits. The objective is a correct mapping of concurrent processes to reconfigurable hardware.

A multi-layer-perceptron neural network hardware based on 3D massively parallel optoelectronic circuits

A digital neural network architecture is presented which is based on three-dimensional massively parallel optoelectronic circuits. A suitable optical interconnect system and the structure of the required electronic circuits is specified. For this system general formulas for the performance of such a neural network architecture are determined. A parameter study using current technological limitations and timing values from electronic implementation is carried out. Based on this analysis if is shown that this novel type of neuroarchitecture that is using 3D massively parallel optoelectronic circuits shows performance rates of up to one magnitude higher than systems using digital neurochips based on fully electronic implementation.

Algorithms for High-Performance Computing with Smart Pixels

One of the major problems in current parallel high-performance computing systems are limitations in the I/O-bandwidth. This is not only a problem on board level communication but also for chip-to-chip and even gate-to-gate interconnections especially in parallel computers. Optical interconnections between in VLSI technology manufactured electronic circuits as aspired in so-called smart pixels systems may offer in the future a solution1. This paper presents well-suited algorithms and architectures for future smart pixels systems consisting of monolithically integrated photodiodes and electronic circuits, which are hybrid mounted to vertical surface emitting laser diodes (VCSEL)2.

Standard cell-based implementation of a digital optoelectronic neural-network hardware

A standard cell-based implementation of a digital optoelectronic neural-network architecture is presented. The overall structure of the multilayer perceptron network that was used, the optoelectronic interconnection system between the layers, and all components required in each layer are defined. The design process from VHDL-based modeling from synthesis and partly automatic placing and routing to the final editing of one layer of the circuit of the multilayer perceptrons are described. A suitable approach for the standard cell-based design of optoelectronic systems is presented, and shortcomings of the design tool that was used are pointed out. The layout for the microelectronic circuit of one layer in a multilayer perceptron neural network with a performance potential 1 magnitude higher than neural networks that are purely electronic based has been successfully designed.

Entwicklung einer abstrakten Speicherkomponente für eine verteilte heterogene dynamische Infrastruktur in Java/CORBA

Da die Entwicklung von Applikationen fur verteilte heterogene dynamische Systeme komplexe Probleme birgt, existieren vielfaltige Werkzeuge, die eine Infrastruktur zur Unterstutzung des Entwicklers bilden. In dieser Arbeit wird eine Speicherkomponente als Bestandteil einer umfassenden Infrastruktur vorgestellt, die eine ortstransparente Datenhaltung mit abstrakten Datentypen ermoglicht. Zur Stei-gerung der Zugriffsgeschwindigkeit konnen lokale Kopien transparent erzeugt werden. Um einen schnellen Datentransport in heterogenen Netzwerken zu gewahrleisten, wird zur Laufzeit aus einer Menge unterstutzter Ubertragungsprotokolle ein jeweils geeignetes gewahlt. Diese Speicherkomponente wurde unter Einsatz einer Kombination von Java und CORBA implementiert. Messungen an einem exemplarischen Testsystem offenbaren den auftretenden Organisationsaufwand.

Verification of Control Paths Using Petri Nets

This work introduces a hardware design methodology based on Petri nets that is applied to the verification of digital control paths. The main purpose is to design control paths that are modeled and verified formally by means of Petri net techniques.

Verification of digital control paths using Petri nets

Introduces a hardware design methodology based on Petri nets that is applied to the verification of digital control paths. The main purpose is to design control paths that are modeled and verified formally by means of Petri net techniques. A verified digital system can be implemented in self-timed or in synchronous clocked hardware modules. Finally, timing analysis can be performed by timed Petri nets.

Integrated optoelectronic reconfigurable digital signal processor using smart-detector technology

We introduce an optoelectronic VLSI implementation of a parallel signal processor whose processing nodes receive their binary constant values by means of an optical interconnection network. The processing nodes are integrated in a fixed array raster. Each node requires its own optical inputs realized as smart-detector units. A smart-detector is a combination of an optical receiver device and a receiver circuit and transforms the optical information into electrical signals. We use integrated photo diodes as optical receivers. The photo diodes are optimized for fiber optical coupling and they can be integrated with standard mainstream CMOS/BiCMOS technology. The project is in progress and we present first results.