M. A. Alam

Material Dependence of NBTI Physical Mechanism in Silicon Oxynitride (SiON) p-MOSFETs: A Comprehensive Study by Ultra-Fast On-The-Fly (UF-OTF) I DLIN Technique

An ultra-fast on-the-fly (UF-OTF) IDLIN technique having 1 mus resolution is developed and used to study gate insulator process dependence of NBTI in silicon oxynitride (SiON) p- MOSFETs. The nitrogen density at the Si-SiON interface and the thickness of SiON layer are shown to impact temperature, time, and field dependencies of NBTI. The plausible material dependence of NBTI physical mechanism is explored.

Separation method of hole trapping and interface trap generation and their roles in NBTI reaction-diffusion model

In this study, we propose a systematic method to separate the hole trapping from measured V1 shift, thus giving the ideal interface trap generation behavior without measurement disturbance. Three stages of interface trap generation have been illustrated with the analytical H-H2 NBTI reaction-diffusion model, and the hole trapping has also been verified with its voltage-enhanced and temperature-insensitive properties. Finally, the PMOS device lifetime extrapolation without considering the hole trapping might lead to significant lifetime overestimation.

Theory and Practice of On-the-fly and Ultra-fast V T Measurements for NBTI Degradation: Challenges and Opportunities

On-the-fly and ultra-fast VT are popular characterization techniques for analyzing NBTI degradation. We show that these techniques do not probe the intrinsic NBTI degradation directly and hence require suitable correction. The corrected data allows us to explore the subtlety of relaxation dynamics by various measurements and suggest a theoretical basis for log-t relaxation consistent within R-D framework.

Ultralocalized thermal reactions in subnanoliter droplets-in-air

Miniaturized laboratory-on-chip systems promise rapid, sensitive, and multiplexed detection of biological samples for medical diagnostics, drug discovery, and high-throughput screening. Within miniaturized laboratory-on-chips, static and dynamic droplets of fluids in different immiscible media have been used as individual vessels to perform biochemical reactions and confine the products. Approaches to perform localized heating of these individual subnanoliter droplets can allow for new applications that require parallel, time-, and space-multiplex reactions on a single integrated circuit. Our method positions droplets on an array of individual silicon microwave heaters on chip to precisely control the temperature of droplets-in-air, allowing us to perform biochemical reactions, including DNA melting and detection of single base mismatches. We also demonstrate that ssDNA probe molecules can be placed on heaters in solution, dried, and then rehydrated by ssDNA target molecules in droplets for hybridization and detection. This platform enables many applications in droplets including hybridization of low copy number DNA molecules, lysing of single cells, interrogation of ligand–receptor interactions, and rapid temperature cycling for amplification of DNA molecules.

Impact of nanowire variability on performance and reliability of gate-all-around III-V MOSFETs

Gate-all-around (GAA) transistors use multiple parallel nanowires to achieve the desired ON current. The fabrication and performance of GAA transistors have been reported, however, a fundamental consideration, namely, the scaling and variability of transistor performance as a function of the number of parallel NWs is yet to be discussed. In this paper, we (i) examine how the overall performance matrix (e.g., ION, IOFF, Vth, SS, RC) depends on the number of parallel NWs, (ii) theoretically interpret the results in terms of variability and self-heating among the NWs, (iii) compare the reliability of multiple NW devices (ΔVth, ΔSS, both stress and recovery) with a planar device of similar technology. We find that the self-heating and NW-to-NW variability are reflected in novel properties of variability and reliability of GAA transistors that are neither anticipated nor observed in the corresponding planar technology.

Light-induced lattice expansion leads to high-efficiency perovskite solar cells

Light relaxes hybrid perovskites Ion migration in organic-inorganic perovskite solar cells limits device stability and performance. Tsai et al. found that a cesium-doped lead triiodide perovskite with mixed organic cations underwent a uniform lattice expansion after 180 min of exposure at 1 sun of illumination. This structural change reduced the energy barriers for charge carriers at the contacts of solar cells. The resulting increase in power conversion efficiency from 18.5 to 20.5% was maintained for more than 1500 hours of illumination. Science, this issue p. 67 Light-induced lattice expansion improves crystallinity and relaxes lattice strain in organic-inorganic perovskite films. Light-induced structural dynamics plays a vital role in the physical properties, device performance, and stability of hybrid perovskite–based optoelectronic devices. We report that continuous light illumination leads to a uniform lattice expansion in hybrid perovskite thin films, which is critical for obtaining high-efficiency photovoltaic devices. Correlated, in situ structural and device characterizations reveal that light-induced lattice expansion benefits the performances of a mixed-cation pure-halide planar device, boosting the power conversion efficiency from 18.5 to 20.5%. The lattice expansion leads to the relaxation of local lattice strain, which lowers the energetic barriers at the perovskite-contact interfaces, thus improving the open circuit voltage and fill factor. The light-induced lattice expansion did not compromise the stability of these high-efficiency photovoltaic devices under continuous operation at full-spectrum 1-sun (100 milliwatts per square centimeter) illumination for more than 1500 hours.

Multi-probe interface characterization of In 0.65 Ga 0.35 As/Al 2 O 3 MOSFET

Through a combination of measurement techniques, we study the interface properties of In_0.65Ga_0.35As transistor with ALD deposited Al₂O₃ gate dielectric. We show that the interface trap density at In_0.65Ga_0.35As/Al₂O₃ interface can be relatively high, but the transistor still exhibits inversion characteristics. A detailed profiling of the interface traps shows that majority of the interface traps are donor-like, and explains the absence of Fermi level pinning in spite of the high interface trap density.

SILC-based reassignment of trapping and trap generation regimes of positive bias temperature instability

We report a simple but effective SILC-based methodology to separate and identify trapping and trap generation dominated regimes of positive bias temperature instability (PBTI). We use theoretical model and experiments to demonstrate that the sign for stress induced leakage current (SILC) reverses as PBTI transitions from trapping to trap generation dominated regimes; this is in contrast to threshold voltage shift with no corresponding sign reversal. SILC crossover methodology further verifies that initial and fast saturated trapping is temperature independent while trap generation is voltage and temperature activated. The SILC-based reassignment not only indentifies trapping and trap generation regimes of PBTI, but also suggests a remarkable universality of trap generation in wide variety of High-k samples.

A comprehensive analysis of off-state stress in drain extended PMOS transistors: Theory and characterization of parametric degradation and dielectric failure

In this paper, we provide the first systematic and comprehensive analysis of off-state degradation in Drain-Extended PMOS transistors - an enabling input/output (I/O) component in many systems and a prototypical example of devices with correlated degradation (i.e., hot carrier damage leading to gate dielectric failure). We use a wide range of characterization tools (e.g., Charge-pumping and multi-frequency charge pumping to probe damage generation, IDLIN measurement for parametric degradation, current-ratio technique to locate breakdown spot, etc.) along with broad range of computational models (e.g., process, device, Monte Carlo models for hot-carrier profiling, asymmetric percolation for failure statistics, etc.) to carefully and systematically map the spatial and temporal dynamics of correlated trap generation in DePMOS transistors. Our key finding is that, despite the apparent complexity and randomness of the trap-generation process, appropriate scaling shows that the mechanics of trap generation is inherently universal. We use the universality to understand the parametric degradation and TDDB of DePMOS transistors and to perform lifetime projections from stress to operating conditions.

Universality of Off-State Degradation in Drain Extended NMOS Transistors

Off-state degradation in drain extended NMOS transistors is studied. It is shown that the damage is primarily due to Si-O bonds broken by hot carriers. These hot carriers are generated through impact ionization of surface band-to-band tunneling (BTBT) current. The resultant degradation is found to be universal, enabling reliability projections at lower stress voltages and based on shorter duration tests, than previously anticipated