M.A. Do

A 1.8-V 6.5-GHz low power wide band single-phase clock CMOS 2/3 prescaler

In this paper, the switching and short-circuit power consumption and the operating frequency of the extended true single-phase clock (E-TSPC) based divide-by-⅔ prescaler is investigated. Based on this analysis, a new ultra low power wide band ⅔ prescaler is proposed and implemented using a GlobalFoundries 0.18 µm CMOS technology. Compared with the existing E-TSPC architectures, the proposed ⅔ prescaler is capable of operating up to 6.5 GHz and eliminates the switching and short circuit power of the first D flip-flop (DFF) during the divide-by-2 operation and also the short-circuit power consumption in the first stage of the second D flip-flop. When compared under the same technology at supply voltage of 1.8-V, a 50% reduction in total power consumption is achieved during divide-by-2 operation. The proposed divide-by-⅔ unit consumes a power of 1 mW and 1.8 mW during divide-by-2 and divide-by-3 modes respectively.

A novel RFCMOS process monitoring test structure

A novel RFCMOS process monitoring test structure has been proposed for the first time in this paper. Excellent agreement in DC and RF characteristics has been observed between conventional test structures and the new process monitoring test structure for both n and p MOSFETs of different device dimensions. This new layout approach can be extended to other devices such as MIM capacitors, diodes, MOS varactors and interconnects.

A Low Power Fully Programmable 1MHz Resolution 2.4GHz CMOS PLL Frequency Synthesizer

This paper presents a low power, high resolution 2.4 GHz CMOS frequency synthesizer for low power wireless LAN applications. The PLL frequency synthesizer consists of a fully programmable frequency divider with a resolution of 1 MHz in the range of 2.4 GHz-2.484 GHz.The measured results showed that the programmable divider consumes 946 uA and Quadrature VCO consumes 1.57 mA and produces output swing of 650-700 mVpp. The complete synthesizer is designed using the Chartered RF 0.18 um process and synthesizer consumes 2.7 mA.

A 1.8-V 3.6-mW 2.4-GHz fully integrated CMOS frequency synthesizer for IEEE 802.15.4

This paper presents a low power 2.4-GHz fully integrated 1 MHz resoltuion IEEE 802.15.4 frequency sysnthesizer designed using 0.18 µm CMOS technology. An integer-N fully programmable divider employs a novel True-single-phase-clock (TSPC) 47/48 prescaler and 6 bit P and S counters to provide the 1MHz output with nearly 45% duty cycle. The PLL uses a series quadrature voltage controlled oscillator (S-QVCO) to generate quadrature signals. The PLL consumes 3.6 mW of power at 1.8 V supply with the fully programmable divider consuming only 600 µW. The S-QVCO consumes 2.8 mW of power with a phase noise of −122.4 dBc/Hz at 1MHz offset.

Extremely high-Q stacked transformer-type inductors for RF applications

A stacked tunable inductor with extremely high quality factor (Q) (>2000) is presented. Compared with transformer-type inductors with interleaved configuration, full-wave electromagnetic (EM) simulation results demonstrate that the stacked structure offers greater advantages in terms of area efficiency, achievable inductance value, and peak Q frequency. Besides, detailed discussions on power levels at the inputs of driving coils are presented to illustrate the effects of parasitic capacitance between the primary coil and driving coil.

A Cascade-Parallel Based Noise De-Embedding Technique for RF Modeling of CMOS Device

In this letter, a unique cascade-parallel based noise de-embedding technique is presented for on-wafer device characterization and modeling. It utilizes two fully shielded THRU line structures and one OPEN structure that enable simultaneously de-embedding of series contact resistance, forward coupling and distributed parasitics of interconnect. Thus, it is more suitable for RF/millimeter wave noise characterization of lossy CMOS devices as compared to conventional lumped and cascade based de-embedding techniques. The proposed noise de-embedding technique is verified on both zero length THRU and OPEN devices. It demonstrates a better high frequency de-embedding performance than existing cascade based techniques by showing 1 dB improvement in predicted NFmin of 0.13 μm CMOS devices at 60 GHz. This is consistent with the further validation result on the de-embedded gain performance of the transistor.

A 2GHz programmable counter with new re-loadable D flip-flop

A high-speed programmable counter with a new re-loadable D Flip-flop which integrates the programmable function to a single true-single-phase-clock (TSPC) D flip-flop is presented. The proposed re-loadable D flip-flop is able to operate at higher frequencies with lower power consumption in comparison to the performance of the existing bitcell. A programmable divide-by-N counter implemented with this re-loadable D flip-flop using the Chartered 0.18 /spl mu/m CMOS process is capable of operating up to 2 GHz for a 1.8 V supply voltage with 4.7 mW power consumption.

A novel de-embedding technique for On-Wafer characterization of RF CMOS

A novel de-embedding technique based on general fixture model is proposed to accurately de-embed the test fixture parasitic for characterization of RF CMOS at high frequency. The method is able to avoid over-de-embedding errors that exist in conventional techniques by utilizing three Thru structures of zero length and one Open dummy test structures for accurate extraction of fixture parasitic. The de-embedding result is verified with Thru line replaced as intrinsic device and has been shown matching closer to the actual intrinsic Thru line than other compared techniques for frequency of up to 50 GHz.

Wide bandwidth Stacked Patch Antenna on Fourteen Layers Microwave Board

A stacked multilayer circular patch antenna with wide bandwidth has been realized on a fourteen layer multilayer microwave board for the first time. The main radiator consists of eight layer disk plates, and the antenna is fed by a conductor-backed coplanar waveguide (CBCPW). The measured results show that the multilayer antenna can operate within 2.8GHz-5.8GHz and have a relative bandwidth of 70%. The antenna has potential application for wireless communications

Design of a Fully Integrated Switchable Transistor CMOS LNA for 2.1 / 2.4 GHz Application

This paper presents a fully integrated switchable transistor CMOS LNA for 2.1 GHz and 2.4 GHz applications. The LNA is designed using 0.18 mum 1P6M CMOS technology. It matches the input in two frequency bands easily without using extra on-chip spiral inductor, compared with (Zhenbiao Li, 2004), (Hashemi, 2001). The post layout simulation exhibits input matching with S11 of -12.9 dB at 2.1 GHz and -24.1 dB at 2.4 GHz respectively. Moreover, it achieves power gain of 14 dB and 14.6 dB, noise figure 3.6 dB and 3.7 dB, and IIP3 -1.3 dBm and 2.6 dBm respectively