Xi Sung Loo

A New Millimeter-Wave Fixture Deembedding Method Based on Generalized Cascade Network Model

In this letter, a universal cascade-based deembedding technique was presented for on-wafer characterization of the RF CMOS device. As compared with existing deembedding approaches, it is developed based on unique combinations of two THRU structures that enable efficient deembedding of fixture parasitics without any inaccurate lumped approximation or requirement of known standards. The proposed deembedding technique is validated on 0.13- μm CMOS devices and has been proven to be more accurate than existing lumped and cascade-based deembedding techniques. As a result, it gives deeper physical prediction on transistor gate capacitances and transconductance. Therefore, it is highly suitable to be applied for device characterization at millimeter-wave frequencies.

An Accurate Two-Port De-Embedding Technique for RF/Millimeter-Wave Noise Characterization and Modeling of Deep Submicrometer Transistors

An accurate and simple noise de-embedding technique is proposed for high-frequency noise characterization of transistors. It is demonstrated on 0.13-μm CMOS devices for up to 80 GHz. The proposed technique adopts a generalized two-port fixture model in conjunction with a set of shielded based structures, which enable simple de-embedding of fixture parasitic for up to the Metal 1 level. Unlike other methods, it is capable of simultaneously accounting for the parasitic effects of probe to pad contact impedances and metal finger parasitic while using only three dummy test structures. Also, it is designed to accommodate nonsymmetry between bond pad parasitic elements at two-port without consuming additional silicon area. This corresponds to a reduction in noise de-embedding error, which increases along the frequency domain (6% of NFmin at 80 GHz). Meanwhile, underestimation of metal finger parasitic by conventional techniques has lead to degradation in noise performance (NFmin) of 0.13-μm CMOS transistors by more than 3.5 dB at 80 GHz. Further validation results from extracted gate capacitance and transistor gain performance provide solid support to the proposed de-embedding technique.

THRU-Based Cascade De-embedding Technique for On-Wafer Characterization of RF CMOS Devices

In this paper, an accurate two-port cascade-based de-embedding technique is presented for characterization of RF devices. It uses two and four structures for device structure with symmetrical and asymmetrical layouts, respectively. Specifically, it outperforms the existing de-embedding techniques by showing distinct capability of accounting for both series contact resistance and distributed effects of interconnects. Furthermore, it is designed to overcome the deficiency of existing transmission line-based techniques in dealing with the interconnects of nonuniform line width. To avoid over de-embedding errors in lumped techniques, the deembedding is performed in unique steps with solely THRU structures for better prediction of test fixture parasitic. The proposed technique is verified on THRU line for a wide frequency range from 2 to 50 GHz. It demonstrates better performance over existing transmission line-based technique as evidenced by excellent agreement with electromagnetic simulation result of THRU line. This is further confirmed by validation result on deembedded gain and gate capacitance of 0.13-μm nMOS devices.

MOSFET Drain Current Noise Modeling With Effective Gate Overdrive and Junction Noise

In this letter, a drain current noise model that includes the channel thermal noise and the shot noise generated at the source-bulk junction and the drain-bulk junction is presented. A unified analytical expression is derived to ensure excellent continuity with smooth transition of drain current noise from weak- to strong-inversion regimes, including the moderate-inversion region. Excellent agreement between simulated and extracted noise data has shown that the proposed model is accurate over different dimensions and operating conditions.

A Cascade-Parallel Based Noise De-Embedding Technique for RF Modeling of CMOS Device

In this letter, a unique cascade-parallel based noise de-embedding technique is presented for on-wafer device characterization and modeling. It utilizes two fully shielded THRU line structures and one OPEN structure that enable simultaneously de-embedding of series contact resistance, forward coupling and distributed parasitics of interconnect. Thus, it is more suitable for RF/millimeter wave noise characterization of lossy CMOS devices as compared to conventional lumped and cascade based de-embedding techniques. The proposed noise de-embedding technique is verified on both zero length THRU and OPEN devices. It demonstrates a better high frequency de-embedding performance than existing cascade based techniques by showing 1 dB improvement in predicted NFmin of 0.13 μm CMOS devices at 60 GHz. This is consistent with the further validation result on the de-embedded gain performance of the transistor.

A novel de-embedding technique for On-Wafer characterization of RF CMOS

A novel de-embedding technique based on general fixture model is proposed to accurately de-embed the test fixture parasitic for characterization of RF CMOS at high frequency. The method is able to avoid over-de-embedding errors that exist in conventional techniques by utilizing three Thru structures of zero length and one Open dummy test structures for accurate extraction of fixture parasitic. The de-embedding result is verified with Thru line replaced as intrinsic device and has been shown matching closer to the actual intrinsic Thru line than other compared techniques for frequency of up to 50 GHz.

A Hybrid Pad-Line-Finger De-Embedding Technique for Broadband Modeling of CMOS Transistor

A hybrid cascade series-parallel based de-embedding technique is presented in this letter for accurate broadband modeling of CMOS transistor. Specifically, it relies on a unique set of PAD-LINE test structures to extract line and pad parasitics without any inaccurate lumped assumptions. Additional FINGER OPEN-SHORT structures are used for further removal of interdigital finger parasitics. As compared to others, it is capable of accounting for metal finger parasitics and distributed effects of metal interconnections plus pad simultaneously. The proposed de-embedding technique has been validated on RF parameters of NMOS device for up to 100 GHz. It has been demonstrated to be more physical than conventional de-embedding approaches and previous work in removal of fixture parasitics for up to metal fingers.

A new unified model for channel thermal noise of deep sub-micron RFCMOS

A new unified model for circuit simulation is presented to predict the high frequency channel thermal noise of deep sub-micron MOSFETs in strong inversion region. Based on the new channel thermal noise model, the simulated channel thermal noise spectral densities of the devices fabricated in a 0.13μm RFCMOS technology process are compared to the channel noise directly extracted from RF noise measurements.

A Novel device for low noise amplification in 130nm high resistivity RFSOI technology platform

CMOS Silicon on Insulator (SOI) is now the technology of choice for RF switches in front end module systems. The emergence of 4G cellular systems with carrier aggregation has made the design of front end modules more complex. To take into account the diversity paths now required in cellular systems the low noise amplifiers (LNAss) are being integrated in the front end module along with the switches. This paper describes novel low noise amplifier devices in high resistivity SOI targeted for integration and use in RF front end modules.

On-Wafer Microwave De-Embedding Techniques

Wireless communication technology has kept evolving into higher frequency regime to take advantage of wider data bandwidth and higher speed performance. Successful RF circuit design requires accurate characterization of on-chip devices. This greatly relies on robust de-embedding technique to completely remove surrounding parasitics of pad and interconnects that connect device to measurement probes. Complex interaction of fixture parasitic at high frequency has imposed extreme challenges to de-embedding particularly for lossy complementary metal oxide semiconductor (CMOS) device. A generalized network de-embedding technique that avoids any inaccurate lumped and transmission line assumptions on the pad and interconnects of the test structure is presented. The de-embedding strategy has been validated by producing negligible deembedding error (<−50 dB) on the insertion loss of the zero-length THRU device. It demonstrates better accuracy than existing de-embedding techniques that are based on lumped pad assumption. For transistor characterization, the de-embedding reference plane could be further shifted to the metal fingers with additional Finger OPEN-SHORT structures. The resulted de-embedded RF parameters of CMOS transistor show good scalability across geometries and negligible frequency dependency of less than 3% for up to 100 GHz. The results reveal the importance of accounting for the parasitic effect of metal fingers for transistor characterization.