L. H. K. Chan

Effects of polysilicon shield on spiral inductors for silicon-based RF IC's

Increasing demands for more affordable personal mobile communication equipment have motivated research and development of low cost, high performance silicon-based on-chip inductors. Current silicon technology uses a conductive substrate, which causes unwanted energy dissipation. Inserting a patterned polysilicon shield beneath inductors can help reduce this substrate loss. Effects of the polysilicon ground shield on inductor performance have been investigated. An inductor utilizing a new high resistivity polysilicon floating shield is shown in this paper to have improved inductive characteristics.

A New Millimeter-Wave Fixture Deembedding Method Based on Generalized Cascade Network Model

In this letter, a universal cascade-based deembedding technique was presented for on-wafer characterization of the RF CMOS device. As compared with existing deembedding approaches, it is developed based on unique combinations of two THRU structures that enable efficient deembedding of fixture parasitics without any inaccurate lumped approximation or requirement of known standards. The proposed deembedding technique is validated on 0.13- μm CMOS devices and has been proven to be more accurate than existing lumped and cascade-based deembedding techniques. As a result, it gives deeper physical prediction on transistor gate capacitances and transconductance. Therefore, it is highly suitable to be applied for device characterization at millimeter-wave frequencies.

An Accurate Two-Port De-Embedding Technique for RF/Millimeter-Wave Noise Characterization and Modeling of Deep Submicrometer Transistors

An accurate and simple noise de-embedding technique is proposed for high-frequency noise characterization of transistors. It is demonstrated on 0.13-μm CMOS devices for up to 80 GHz. The proposed technique adopts a generalized two-port fixture model in conjunction with a set of shielded based structures, which enable simple de-embedding of fixture parasitic for up to the Metal 1 level. Unlike other methods, it is capable of simultaneously accounting for the parasitic effects of probe to pad contact impedances and metal finger parasitic while using only three dummy test structures. Also, it is designed to accommodate nonsymmetry between bond pad parasitic elements at two-port without consuming additional silicon area. This corresponds to a reduction in noise de-embedding error, which increases along the frequency domain (6% of NFmin at 80 GHz). Meanwhile, underestimation of metal finger parasitic by conventional techniques has lead to degradation in noise performance (NFmin) of 0.13-μm CMOS transistors by more than 3.5 dB at 80 GHz. Further validation results from extracted gate capacitance and transistor gain performance provide solid support to the proposed de-embedding technique.

Substrate-Induced Noise Model and Parameter Extraction for High-Frequency Noise Modeling of Sub-Micron MOSFETs

In this paper, a substrate-induced drain-current noise model is developed in addition to the channel thermal noise to explain the non-white-noise characteristic found in the measured drain-current noise in the gigahertz range. The substrate-induced drain-current noise model is derived from the proposed small-signal equivalent circuit with a substrate coupling network and a substrate thermal noise source. The model parameter extraction method utilizing Y-parameter analysis on the proposed small-signal equivalent circuit is demonstrated. The model for the total drain-current noise, the gate-current noise, their cross-correlation, and thereafter the four noise parameters is presented and verified experimentally. Excellent agreement between simulated and measured noise data has been obtained over different dimensions and operating conditions.

MOSFET Drain Current Noise Modeling With Effective Gate Overdrive and Junction Noise

In this letter, a drain current noise model that includes the channel thermal noise and the shot noise generated at the source-bulk junction and the drain-bulk junction is presented. A unified analytical expression is derived to ensure excellent continuity with smooth transition of drain current noise from weak- to strong-inversion regimes, including the moderate-inversion region. Excellent agreement between simulated and extracted noise data has shown that the proposed model is accurate over different dimensions and operating conditions.

A Cascade-Parallel Based Noise De-Embedding Technique for RF Modeling of CMOS Device

In this letter, a unique cascade-parallel based noise de-embedding technique is presented for on-wafer device characterization and modeling. It utilizes two fully shielded THRU line structures and one OPEN structure that enable simultaneously de-embedding of series contact resistance, forward coupling and distributed parasitics of interconnect. Thus, it is more suitable for RF/millimeter wave noise characterization of lossy CMOS devices as compared to conventional lumped and cascade based de-embedding techniques. The proposed noise de-embedding technique is verified on both zero length THRU and OPEN devices. It demonstrates a better high frequency de-embedding performance than existing cascade based techniques by showing 1 dB improvement in predicted NFmin of 0.13 μm CMOS devices at 60 GHz. This is consistent with the further validation result on the de-embedded gain performance of the transistor.

High-Frequency Noise Modeling of MOSFETs for Ultra Low-Voltage RF Applications

In this paper, analytical models for high-frequency drain-current noise, gate-current noise, and their cross-correlation of MOSFETs are presented with an emphasis on the weak- and moderate-inversion regions. Unified expressions offering excellent continuity and smoothness from weak- to moderate- and strong-inversion regimes were developed. It is demonstrated that the continuity and the accuracy of the calculated four noise parameters, such as minimum noise figure, normalized noise resistance, and optimum source conductance and susceptance, are significantly improved in the weak- and moderate-inversion regions by using the proposed unified noise model, which includes the junction-induced drain-current noise. A figure-of-merit is introduced to determine the optimum gate biasing point of MOSFETs, where high gain can be achieved at low driving power and low operating noise. The results obtained from the proposed model manifest good agreement with the on-wafer measurement results.

A novel de-embedding technique for On-Wafer characterization of RF CMOS

A novel de-embedding technique based on general fixture model is proposed to accurately de-embed the test fixture parasitic for characterization of RF CMOS at high frequency. The method is able to avoid over-de-embedding errors that exist in conventional techniques by utilizing three Thru structures of zero length and one Open dummy test structures for accurate extraction of fixture parasitic. The de-embedding result is verified with Thru line replaced as intrinsic device and has been shown matching closer to the actual intrinsic Thru line than other compared techniques for frequency of up to 50 GHz.

A new unified model for channel thermal noise of deep sub-micron RFCMOS

A new unified model for circuit simulation is presented to predict the high frequency channel thermal noise of deep sub-micron MOSFETs in strong inversion region. Based on the new channel thermal noise model, the simulated channel thermal noise spectral densities of the devices fabricated in a 0.13μm RFCMOS technology process are compared to the channel noise directly extracted from RF noise measurements.