M. Amimul Ehsan

An Analytical Through Silicon Via (TSV) Surface Roughness Model Applied to a Millimeter Wave 3-D IC

In the millimeter wave (mmW) frequency range, the root mean square height of the through silicon via (TSV) sidewall roughness is comparable to the skin depth, and hence, becomes a critical factor for TSV modeling and analysis. In this paper, the impact of the TSV sidewall roughness on electrical performance, such as the loss and impedance alteration in the mmW frequency range, is examined and analyzed. The second-order small analytical perturbation method is applied to obtain a simple closed-form expression for the power absorption enhancement factor of the TSV. In this study, we propose an electrical model of the TSV, which considers the TSV sidewall roughness effect, the skin effect, and the metal oxide semiconductor effect. The parameters of the proposed circuit model can be determined analytically; the accuracy of the model is validated through a comparison of circuit model behavior for full wave electromagnetic field simulations up to 100 GHz.

Electrical modeling and analysis of sidewall roughness of through silicon vias in 3D integration

Electrical modeling of through silicon via (TSV) is very important for three dimensional (3D) system design and analysis. In this paper, we present our study on the impact of sidewall roughness on the TSV electrical performance in the ultra-broad band range. Our analysis shows that the root mean square height of the rough sidewall is comparable to the skin depth in extremely high frequency (> 20G HZ). Therefore, the effect of TSV sidewall roughness becomes one of the critical factors to be considered when modeling TSV in extremely high frequency band. An electrical model of TSV is proposed considering the effect of TSV sidewall roughness, as well as capturing the high frequency skin effect. The proposed circuit model is analytically calculated and validated with EM field simulations up to 50 GHz.

Design challenges and methodologies in 3D integration for neuromorphic computing systems

Neuromorphic computing is an emerging technology that describes the biological neural systems and implementation of its electrical model in complementary metal-oxide-semiconductor (CMOS) VLSI systems. As the neural networks are wire dominated complicated system with myriad interconnected elements, it requires massively parallel processing for the computational task. However, the hardware implementation experiences some critical challenges and unsurmountable obstacles by using 2D planar circuits. Therefore, the potential three dimensional integration technology can be applied in hardware implementation of neuromorphic computing that provides a sustainable and promising alternative to the existing conventional integrated circuit (IC) technology by allowing vertical stacking of dies. 3D hardware interconnection between the neural layers not only offer high device interconnection density with greater reduction in parasitic, it also provides improved channel bandwidth using fast and energy efficient links with excellent distribution and communication among the neuron layers. Beyond these opportunities, it needs a thorough investigation to explore all the design issues and critical challenges for successful implementation of 3D neuromorphic computation for high performance application. In this work, we studied the design challenges of the 3D integration technology for neuromorphic computing systems, and possible ways to overcome the limitation of well-connected synaptic system.

Electrical modeling and analysis of 3D synaptic array using vertical RRAM structure

Three-dimensional (3D) integrated circuits (ICs) offer a promising near-term solution for pushing beyond Moores Law because of their compatibility with current technology while providing high system speed, high density, massively parallel processing, low power consumption, and a small footprint. In this paper, a novel 3D neuromorphic IC architecture combining monolithic 3D integration and vertical resistive random-access memory (V-RRAM) technology is proposed. Furthermore, a concise equivalent circuit model of the proposed structure is created and the analytical calculation for each parameter in the equivalent circuit is provided. The electrical performance of the proposed 3D neuromorphic computing structure is evaluated through SPICE simulations.

Modeling and optimization of TSV for crosstalk mitigation in 3D neuromorphic system

Neuromorphic computing is an emerging technology that describes the biological neural systems and implementation of its electrical model in complementary metal-oxide-semiconductor (CMOS) VLSI system. Three dimensional (3D) integration can be applied in hardware implementation of neuromorphic computing that provides high device interconnection density using fast and energy efficient links with excellent distribution and communication among the neuron layers. In this work, we studied the necessities of neuromorphic computing based on 3D integration technology, design challenges, and a possible solution to overcome the effect of huge parallelism of well-connected synaptic system. Using the force directed optimization algorithm, an optimal interconnect array pattern is identified for a proposed structure that could mitigate significant amount of crosstalk. For the analysis of crosstalk, an electrical model of the optimal array structure is proposed and it has been validated by comparing its simulation results with those extracted from commercial tools. This work can be used as a basis study for successful implementation of next generation 3D neuromorphic computation for high performance application.

Electrical modeling and analysis of 3D Neuromorphic IC with Monolithic Inter-tier Vias

Neuromorphic computing is an emerging computing technology which utilizes very-large-scale integration (VLSI) technology to mimic neuro-biological architectures present in the nervous system. It promises the realization of parallel computing with extremely low power consumption. To fully take advantage of this computing technology, its scalability and complexity need to be extended beyond its current two dimensional (2D) CMOS fabrication and package technology. In this paper, a three dimensional integrated circuit (3D-IC) technology, which employs Monolithic Inter-tier Via (MIV) and memristor, is proposed to further miniaturize the system and reduce the power consumption. In this work, the building block of the 3D-IC is modeled. In addition, the impact of the crosstalk between the memristor and the MIV is discussed

Hybrid three-dimensional integrated circuits: A viable solution for high efficiency Neuromorphic Computing

This work details how a neuromorphic system is simulated with a 3D integrated electronic system. The neural system is modeled as a 3D integrated circuit to investigate a highly efficient neuromorphic computing system that ameliorates implementation issues induced by prior 2D circuital systems. A 3D neuronal model incorporating the Through Silicon Via (TSV) is constructed and the performance is simulated. We maintain this work is a competent potential foundation towards a practical design methodology for producing 3D Neuromorphic Computing (NC) circuits and systems that function with lower power consumption, reduced delay, and more advanced system volumetric miniaturization than contemporary systems provide.

Adaptation of Enhanced TSV Capacitance as Membrane Property in 3D Brain-inspired Computing System

Neurophysiological architecture using 3D integration technology offers a high device interconnection density as well as fast and energy efficient links among the neuron and synapses layers. In this paper, we propose to reconfigure the Through-Silicon-Vias (TSVs) to serve as the neuronal membrane capacitors that map the membrane electrical activities in a hybrid 3D neuromorphic system. We also investigate new methodology that could significantly enhance the TSV capacitance to achieve a high efficiency of signal processing through membrane. An optimal CAD framework is designed to optimally utilize such TSV devices, and resolve the signal-integrity issues arising at fast data rates during massively parallel data transmissions. The electrical performance of the 3D neuromorphic chip is compared against the ones of the 2D counterpart design to demonstrate the advantages of our design and methodology.

A Novel Approach for Using TSVs As Membrane Capacitance in Neuromorphic 3-D IC

An advanced neurophysiological computing system can incorporate a 3-D integration system composed of emerging nano-scale devices to provide massive parallelism having high speed, low cost, and energy efficient hardware implementation. Due to process technology constraints, a certain amount of redundant through silicon vias (TSVs) and dummy TSVs are always required in a 3-D integrated system. In this paper, we propose to use these redundant and dummy TSVs to supply the neuronal membrane capacitance that maps the membrane electrical activity in a hybrid 3-D neuromorphic system. This proposition could also serve the need of neuronal ion transportation dynamics. We also investigate two new methodologies that could significantly enhance the TSV capacitance in a 3-D neuromorphic system. The capacitance of these enhanced TSVs is studied with analytical models; the accuracy of the models are evaluated against 3-D field extracted values. The advantage of using the TSVs to mimic membrane capacitance in a 3-D neuromorphic chip is demonstrated through comparisons of both silicon area and energy consumption against their 2-D counterpart designs.

Modeling and analysis of neuronal membrane electrical activities in 3d neuromorphic computing system

Three dimensional (3D) integration technology merged with neuromorphic computing system plays a significant role for the implementation of energy efficient advanced neurobiological architecture. This work explores a novel 3D neuromorphic system that utilizes the Through Silicon Via (TSV) interconnects to build the complicated hardware neural structure. It allows the ultra-high density integrated system and imitates the neuronal membrane electrical activity in a hybrid 3D neuromorphic system. In our designed 3D neuromorphic structure, we extend the innovation in neuronal ion transportation dynamics through the membrane channels using TSVs. The commensal ionic model of a neuronal membrane is developed utilizing the TSV property and the characteristics of the ionic electrical activity through the TSV is determined. Having massively parallel TSVs and configuring them into useful capacitors, the proposed approach could significantly enhance the signal integrity, reduce crosstalk, and thus leverage the heterogeneous integration of 3D neuromorphic IC. The accuracy of the proposed analytical model is evaluated through the comparison of the model giving values to their 3D field extracting values and SPICE simulations.