M. Bhaskar

Synchronization of on-chip serial interconnect transceivers using Delay Locked Loop (DLL)

In literature delay locked loop (DLL) architecture is used for synchronizing the on-chip serial interconnect transceivers instead of phase locked loops (PLL) due to increased stability and low jitter. In this paper, the design and implementation of a Mixed-Delay Locked Loop (DLL) for on-chip serial transceiver is carried out with a modified architecture, which takes less number of clock cycle for locking and has low jitter. The voltage controlled delay line (VCDL) of the proposed DLL is designed with current-starved inverters, which are normally used in PLLs. The charge pump with symmetric load is used to obtain wide frequency range of operation. The proposed DLL circuit is implemented in UMC 0.18µm technology and the post-layout simulations are carried out in CADENCE Spectre tool. From the simulations, it is observed that the proposed mixed DLL circuit operates to the frequency ranges from 650 MHz to 1.2 GHz with a locking period of 4 to 8 clock cycles and has a jitter of approximately 10 psec.

Low power, high performance current mode transceiver for Network-on-Chip communication

In literature, for network on-chip communications, voltage mode and current mode transceivers have been proposed to achieve high performance. In voltage mode transceivers the signal swing is more, which makes the link power high and also limits the bandwidth. Hence, the current mode signaling can be a solution for better performance than voltage mode signaling in terms of delay and power. This paper presents a modified low power, high performance current mode transceiver, which suits for network on chip communication (NoC). The proposed transceiver circuit is implemented in UMC 180nm technology using Cadence spectre tool. From the post layout simulations, it is observed that, the proposed transmitter circuit has a signal swing of 80mV, which is 1.5 times less for normal transistor sizes comparing to the existing circuit. The proposed current mode sense amplifier, which acts as a receiver is able to sense up to an input signal swing of 20mV, which is less by a factor of 2.5 than the reported circuit. The delay of the proposed current mode sense amplifier is less than 50psec, where as for the receiver reported in literature it is 80psec.

A wide band voltage mode sense amplifier receiver for high speed interconnects

In this paper, a novel architecture is proposed for a voltage mode sense amplifier in the receiver for high speed interconnects. This is designed with the objective of achieving higher speed and wider bandwidth than those already reported in the literature. In the conventional voltage mode sense amplifier, the drains of the input transistors are connected to the sense nodes of the cross coupled inverters. In the proposed voltage mode sense amplifier, the drain of the input transistors are directly connected to the output of cross coupled inverters. This reduces the number of series transistors in the evaluation path and hence it reduces the switching times. Effectiveness of this technique is studied through simulation with Synopsys HSPICE using 180 nm technology models. The results obtained are compared with those obtained using the conventional voltage mode sense amplifier and also with that obtained using current mode sense amplifier. From the simulation results, it is found that the proposed voltage mode sense amplifier has a bandwidth which is twice that of conventional voltage mode sense amplifier. Current mode sense amplifier dissipates about six times more power than the proposed voltage mode sense amplifier to achieve identical bandwidth and delay. The proposed amplifier has a bandwidth of 11.6 GHz and a delay of 20 ps in 0.18 mum technology.

Design of a novel differential on-chip wave-pipelined serial interconnect with surfing

In the literature, surfing technique has been proposed for single ended wave-pipelined serial interconnects to increase the data transfer rate. This uses uniform repeaters (UR). In this paper, two novel surfing techniques, one using uniform repeaters (UR) and another using non-uniform repeaters (NUR) are proposed for differential wave-pipelined serial interconnects. The method of logical effort is also proposed for the design of both UR and NUR. To evaluate the efficiency of these techniques, 40mm metal 4 interconnects using the proposed surfing techniques are implemented along with transmitter, receiver and delay locked loop(DLL) in UMC 180nm technology and their performances are studied through post layout simulations. From this study, it is observed that the differential surfing technique using UR and NUR achieve 3.0 times and 4.15 times higher data rates respectively compared to the single ended scheme whose maximum data rate is 1.33GB/s.

Design and implementation of surfing scheme to wave pipelined differential serial interconnect

In literature, surfing scheme has been used in wave pipelined serial interconnects to decrease the delay and ensure transmission reliability. In this paper, a “Controllable inverter pair” is proposed for surfing the differential wave pipelined serial interconnects. The proposed surfing scheme is implemented in UMC 0.18µm technology and the post layout performance is studied through simulation in Cadence spectre tool. The performance of the new scheme is compared with that of a single ended wave-pipelined link with surfing. The proposed scheme permits the data transmission rate of 2.78Gbps and it is higher by a factor of 2.08 compared to the single ended scheme. It also does not require any set up time constraints unlike single ended scheme, where the surfing signal must be ascertained before the data signal about one fourth of the data period.

An input multiplexed current mode transmitter for on-chip global interconnects

In the literature, both current mode and voltage mode multiplexers are proposed for transmitters used to drive global interconnects. Current mode multiplexers operate at higher speeds at the cost of increase in power dissipation. In this paper, a novel technique is proposed to increase the operating speed of the current mode multiplexer by reducing the impedance at the output of the multiplexer. This is achieved by connecting a diode connected transistor as the load. The proposed transmitter is implemented using 180 nm technology and studied through simulation with Synopsys HSPICE assuming an interconnect of length 7 mm. It is found through simulation, that the interconnect driven by this transmitter has a lower delay by a factor of two compared to that obtained using repeater insertion technique. The proposed transmitter is also compared with that using output multiplexing scheme. It is found that the operating bandwidth of the proposed transmitter is two and half times more than that of output multiplexed transmitter. Both rise time and power dissipation are lower by a factor of two for the proposed transmitter compared to the output multiplexed transmitter with four inputs.

FPGA Implementation of a Novel Area Efficient FFT Scheme Using Mixed Radix FFT

In the literature, mixed radix FFT scheme has been proposed to facilitate the computation of FFT in parallel using multiple lower radix FFT modules. Alternately, the speed of the FFT can be increased using Radix-2 decimation-in-frequency (DIF) FFT algorithm with Multipath Delay Commutator (R2MDC) architecture. In this paper, a novel FFT scheme which combines the R2MDC architecture with the serial version of mixed radix FFT scheme is proposed. To study the efficacy of this approach, an 8-point FFT is implemented using R2MDC architecture. Using this, 16-point, 32-point and 64-point FFTs are realized with the serial version of mixed radix scheme and also using only R2MDC architecture on Xilinx Virtex-5 FPGA. From the implementation results, it is found that the hardware requirement for the proposed approach reduces by 25%–53% at the cost of speed compared to the other schemes reported in the literature including that using only R2MDC architecture. The proposed scheme is preferred for low sampling rate applications such as biomedical signal processing.

Reference table based cache design using LRU replacement algorithm for Last Level Cache

The advancements in the field of VLSI design allow multiple cores to be integrated on a single microprocessor chip. With the saturation in the scaling down of transistors to increase speed and performance, it is highly imperative to develop multi-core architectures for increased performance. But the increase in the core count per chip makes it more critical to design an efficient memory sub-system especially for the last level cache (LLC) that is shared among all the cores in a processor. The efficient utilization of the LLC is a dominant method to achieve the best microprocessor throughput. In this paper, the Reference Table (RT) based cache design for LLC of multi-core microprocessor is proposed using LRU replacement policy. The proposed RT Cache design adjusts itself based on the workload and automatically changes the utilization of the cache blocks to cope with the changes in the set access pattern so as to decrease the number of conflict misses. Also, at the same time it takes the advantage of accessing multiple cache blocks simultaneously so as to facilitate fast cache search of the set-associative LLC. The proposed architecture has been tested for a four core x86 multi-core architecture using Multi2sim open source tool. It is observed from the simulations that the proposed design provides an increase of 15.16% in cycles per second and 2.28% increase in hit ratio for L2 cache as compared to the n-way set associative cache.

Design of differential voltage mode transmitter for on-chip serial link based on method of logical effort

In the literature, voltage mode and current mode multiplexers are used for differential on-chip global interconnect transmitters. Conventionally, the Pseudo-NMOS multiplexer used in voltage mode transmitters consumes more power and has less bandwidth, whereas the current mode multiplexers operate at higher speeds at the cost of increase in power consumption. In this paper, a novel domino logic based multiplexer is proposed for differential voltage mode serial interconnect transmitter to minimize the power consumption and the speed comparable to that of current mode multiplexers. The proposed transmitter is designed using the method of logical effort and is implemented in UMC 180nm technology. The post layout simulations are carried out through Cadence Virtuso tool. From the post layout simulations, it is observed that the power consumed and the area of the proposed domino logic based multiplexer is 1.42 times and 3.77 times lower respectively and the speed comparable to that of CMOS multiplexer circuit.

A low power, low latency tunable Quasi-resonant interconnect using active inductor

In literature, to obtain low power, low latency and high performance interconnects, Quasi-resonance concept is implemented with a series spiral inductor. In this paper Quasi-resonant serial interconnect link with a tunable active inductor is proposed to obtain low power, low latency and low area. The proposed scheme is implemented in a UMC 0.18-µm CMOS technology and the post layout simulations are carried out. The performance evaluation is done for 5mm interconnect with a serial data rate of 5Gbps. From simulations, the insertion point and the value of inductor for the minimum power-delay product is obtained. The observed delay and power of the serial link is 290 psec and 13.52 mW, which is less by a factor of 1.27 and 1.87 than the conventional repeater insertion respectively. The area of the active inductor is 1904µm2, which is less by a factor of 3.53 compared to spiral inductor scheme. The proposed scheme has the advantage to tune the interconnect, for data rates from 1Gbps to 5Gpbs by varying the bias voltages of the tunable active inductor.