M. Bobrek

PHENIX inner detectors

Abstract The timing, location and particle multiplicity of a PHENIX collision are determined by the Beam–Beam Counters (BBC), the Multiplicity/Vertex Detector (MVD) and the Zero-Degree Calorimeters (ZDC). The BBCs provide both the time of interaction and position of a collision from the flight time of prompt particles. The MVD provides a measure of event particle multiplicity, collision vertex position and fluctuations in charged particle distributions. The ZDCs provide information on the most grazing collisions. A Normalization Trigger Counter (NTC) is used to obtain absolute cross-section measurements for p–p collisions. The BBC, MVD and NTC are described below.

High density interconnect multi-chip module for the front-end electronics of the PHENIX/MVD

A multi-chip module (MCM) based on High Density Interconnect (HDI) technology was developed for the front-end electronics of a high energy nuclear physics experiment to process charge pulses from silicon detectors. Stringent requirements in performance as well as low radiation length and minimum physical size of the module dictated the use of the most sophisticated MCM technology available. The module handles 256 input channels on an alumina substrate with milled cavities for die placements and four layers of thin-film traces of 42u width. A total of 20 custom integrated circuit chips and 98 passive components are assembled on a substrate of size 43 mm/spl times/48 mm. Various aspects of development efforts for the design and fabrication as well as the electrical test results of the module are discussed.

The PHENIX Multiplicity and Vertex Detector

Abstract We describe the design and expected performance of the PHENIX Multiplicity and Vertex Detector (MVD) sub-system of the PHENIX detector at the Relativistic Heavy Ion Collider (RHIC).

A high resolution, extended temperature sigma delta ADC in 3.3 V 0.5 /spl mu/m SOS-CMOS

A /spl Sigma//spl Delta/ modulator designed specifically for extended temperature applications is reported. The design is fabricated in a 3.3-V 0.5 /spl mu/m SOS-CMOS process and incorporates a 2-2 cascade architecture allowing operation as either a 2/sup nd/- or 4/sup th/-order modulator. Experimental data for both modulator configurations are presented including dynamic range (or effective resolution), signal-to-noise ratio and total harmonic distortion over a temperature range of 25/spl deg/C to 225/spl deg/C. The design obtains an effective resolution of /spl sim/16 bits at 25/spl deg/C and /spl sim/12 bits at 225/spl deg/C, both at a digital output rate of 2 KS/s. Specific design details associated with high temperature operation are discussed including architectural issues, device sizing, and modulator noise. In addition, a digital decimation filter designed for use with the modulator and implemented in both software and in a field programmable gate array is summarized. This paper reports the first 4/sup th/-order /spl Sigma//spl Delta/ modulator fabricated in an SOI/SOS process and demonstrates the feasibility of high resolution data conversion at elevated temperatures.