M.S. Emery

PHENIX inner detectors

Abstract The timing, location and particle multiplicity of a PHENIX collision are determined by the Beam–Beam Counters (BBC), the Multiplicity/Vertex Detector (MVD) and the Zero-Degree Calorimeters (ZDC). The BBCs provide both the time of interaction and position of a collision from the flight time of prompt particles. The MVD provides a measure of event particle multiplicity, collision vertex position and fluctuations in charged particle distributions. The ZDCs provide information on the most grazing collisions. A Normalization Trigger Counter (NTC) is used to obtain absolute cross-section measurements for p–p collisions. The BBC, MVD and NTC are described below.

A multi-channel ADC for use in the PHENIX detector

A custom CMOS analog to digital converter was designed and a prototype 8-channel ADC ASIC was fabricated in a 1.2 /spl mu/m process. The circuit uses a Wilkinson-type architecture which is suitable for use in multi-channel applications such as the PHENIX detector. The ADC design features include a differential positive-ECL input for the high speed clock and selectable control for 11 or 12-bit conversions making it suitable for use in multiple PHENIX subsystems. Circuit topologies and ASIC layout specifics, including power consumption, maximum clock speed, INL, and DNL are discussed. The ADC performed to 11-bit accuracy.

Monolithic circuits for the WA98 lead class calorimeter

Two monolithic circuits developed for readout of a 10000 element lead glass calorimeter are described. The first contains 8 channels with each channel comprising a charge integrating amplifier, two output amplifiers with gains of one and eight, a timing filter amplifier and a constant fraction discriminator. This IC also contains a maskable, triggerable calibration pulser and circuits needed to form 2 by 2 and 4 by 4 energy sums used to provide trigger signals. The second IC is a companion to the first and contains 16 analog memory channels with 16 cells each, eight time-to-amplitude converters and a 24-channel analog-to-digital converter. The use of the analog memories following the integration function eliminates the need for delay cables preceding it. Characterizations of prototypes are reported, and features included to ease integration of the ICs into a readout system are described.<<ETX>>

A modular straw drift tube tracking system for the Solenoidal Detector Collaboration experiment Part I. Design

Abstract We have developed the baseline design for a straw drift tube tracking system for the Solenoidal Detector Collaboration (SDC) detector. The system was designed to operate in the high-rate environment of a high luminosity hadron collider. We present an overview of the tracking system and the requirements it was expected to fulfill. We describe the construction and properties of the straw drift tubes. We discuss the design of the carbon-fiber foam-laminate shell, which supported the wire tension and held the straws in alignment. We also present descriptions of the designs of the front-end and digitization electronics as well as the electronics associated with the level 1 track trigger.

Design and performance of beam test electronics for the PHENIX Multiplicity Vertex Detector

The system architecture and test results of the custom circuits and beam test system for the Multiplicity-Vertex Detector (MVD) for the PHENIX detector collaboration at the Relativistic Heavy Ion Collider (RHIC) are presented in this paper. The final detector per-channel signal processing chain will consist of a preamplifier-gain stage, a current-mode summed multiplicity discriminator, a 64-deep analog memory (simultaneous read-write), a post-memory analog correlator, and a 10-bit 5 /spl mu/s ADC. The Heap Manager provides all timing control, data buffering, and data formatting for a single 256-channel multi-chip module (MCM). Each chip set is partitioned into 32-channel sets. Beam test (16-cell deep memory) performance for the various blocks will be presented as well as the ionizing radiation damage performance of the 1.2 /spl mu/ n-well CMOS process used for preamplifier fabrication.

A multiplicity-vertex detector for the PHENIX experiment at RHIC

Abstract A Multiplicity-Vertex Detector (MVD) has been designed, and is in construction for the PHENIX Experiment at the Relativistic Heavy Ion Collider (RHIC). The 35 000 channel silicon detector is a two-layer barrel comprised of 112 strip detectors, and two disk-shaped endcaps comprised of 24 wedge-shaped pad detectors. The support structure of the MVD is very low mass, only 0.4% of a radiation length in the central barrel. The detector front-end electronics are a custom CMOS chip set containing preamplifier, discriminator, analog memory unit, and analog-to-digital converter. The system has pipelined acquisition, performs in simultaneous read/write mode, and is clocked by the 10 MHz beam crossing rate at RHIC. These die, together with a pair of commercial FPGAs that are used for control logic, are packaged in a mutlichip-module (MCM). The MCM will be fabricated in the High-Density-Interconnect (HDI) process. The prototype MCM design layout is described.

A configurable CMOS voltage DAC for multichannel detector systems

A CMOS voltage DAC has been developed for integration into multiple front-end electronics ASICs associated with the PHENIX detector located at the RHIC accelerator of Brookhaven National Laboratory. The topology allows wide-range output programmability by selection of an offset voltage and on-chip resistor and transistor sizing. The DAC is trimless and requires no external components, making it ideal for highly integrated collider detector systems. Errors associated with on-chip bias are minimized using a topology that implements a ratiometric relationship which compensates for absolute resistance value changes and is limited only by errors in the on-chip matching of MOSFETs and resistive devices. Temperature-induced errors associated with the integrated resistors are also minimized by the circuit topology and monolithic construction. All reference voltages and currents are derived using a single regulated voltage supply. This paper presents the general DAC architecture and design method, discusses on-chip matching issues and tradeoffs associated with device sizing and monolithic layout, and presents measured performance of various gate length DACs fabricated in a 1.2 /spl mu/m CMOS process including integral nonlinearity, differential nonlinearity, and slope and offset errors.

Coherent imaging with two-dimensional focal-plane arrays: design and applications.

Scanned, single-channel optical heterodyne detection has been used in a variety of lidar applications from ranging and velocity measurements to differential absorption spectroscopy. We describe the design of a coherent camera system that is based on a two-dimensional staring array of heterodyne receivers for coherent imaging applications. Experimental results with a single HgCdTe detector translated in the image plane to form a synthetic two-dimensional array demonstrate the ability to obtain passive heterodyne images of chemical vapor plumes that are invisible to normal video infrared cameras. We describe active heterodyne imaging experiments with use of focal-plane arrays that yield hard-body Doppler lidar images and also demonstrate spatial averaging to reduce speckle effects in static coherent images.

High density interconnect multi-chip module for the front-end electronics of the PHENIX/MVD

A multi-chip module (MCM) based on High Density Interconnect (HDI) technology was developed for the front-end electronics of a high energy nuclear physics experiment to process charge pulses from silicon detectors. Stringent requirements in performance as well as low radiation length and minimum physical size of the module dictated the use of the most sophisticated MCM technology available. The module handles 256 input channels on an alumina substrate with milled cavities for die placements and four layers of thin-film traces of 42u width. A total of 20 custom integrated circuit chips and 98 passive components are assembled on a substrate of size 43 mm/spl times/48 mm. Various aspects of development efforts for the design and fabrication as well as the electrical test results of the module are discussed.

Timing and control requirements for a 32-channel AMU-ADC ASIC for the PHENIX detector

A custom CMOS Application Specific Integrated Circuit (ASIC) has been developed consisting of an analog memory unit (AMU) and analog to digital converter (ADC), both of which have been designed for applications in the PHENIX experiment. This IC consists of 32 pipes of analog memory with 64 cells per pipe. Each pipe also has its own ADC channel. Timing and control signal requirements for optimum performance are discussed in this paper.