M-C. Frank Chang

Power reduction of CMP communication networks via RF-interconnects

As chip multiprocessors scale to a greater number of processing cores, on-chip interconnection networks will experience dramatic increases in both bandwidth demand and power dissipation. Fortunately, promising gains can be realized via integration of radio frequency interconnect (RF-I) through on-chip transmission lines with traditional interconnects implemented with RC wires. While prior work has considered the latency advantage of RF-I, we demonstrate three further advantages of RF-I: (1) RF-I bandwidth can be flexibly allocated to provide an adaptive NoC, (2) RF-I can enable a dramatic power and area reduction by simplification of NoC topology, and (3) RF-I provides natural and efficient support for multicast. In this paper, we propose a novel interconnect design, exploiting dynamic RF-I bandwidth allocation to realize a reconfigurable network-on-chip architecture. We find that our adaptive RF-I architecture on top of a mesh with 4B links can even outperform the baseline with 16B mesh links by about 1%, and reduces NoC power by approximately 65% including the overhead incurred for supporting RF-I.

A 1.8-V 6/9-GHz switchable dual-band quadrature LC VCO in SiGe BiCMOS technology

This paper presents a quadrature VCO that can be reconfigured between 6 and 9 GHz frequency bands. The dual-band VCO comprises a 6 GHz LC VCO, two 1/2-dividers, two mixers, and two 3 GHz notch filters. The 9 GHz output is generated based on a fractional frequency multiplication method by mixing the 6 GHz VCO output with its divide-by-two signal. The VCO, implemented in a 0.18 /spl mu/m SiGe BiCMOS technology, shows a fast switching time of 3.6 nsec. The measured VCO phase noises are -106 dBc/Hz and -104 dBc/Hz at 1 MHz offset for 6 and 9 GHz modes, respectively, while draining 10.8 mA from a 1.8 V supply.

A 1.3-GHz IF digitizer using a 4/sup th/-order continuous-time bandpass /spl Delta//spl Sigma/ modulator

We present a 4/sup th/-order, 3-bit, 4.3 GHz continuous-time bandpass /spl Delta//spl Sigma/ modulator (CT-DSM) that can directly digitize a 1.3-GHz IF signal. We used the impulse-invariant transform to design the CT-DSM, which has a similar NTF (noise transfer function) as an idealized discrete-time modulator despite up to 1.6 clock delays in its feedback loop paths. The part was fabricated using InP HBT technology, and has a measured SNDR of 39 dB in a 200 MHz bandwidth.

A 2-Gb/s/pin source synchronous CDMA bus interface with simultaneous multi-chip access and reconfigurable I/O capability

A simultaneous reconfigurable multi-chip access bus interface for application in high-bandwidth multi-drop parallel interconnections such as a memory bus has been developed. The interface utilizes a source synchronous signaling and direct-sequence code-division multiple access (CDMA) technique for high bus concurrency and low channel latency. The prototype chip, fabricated in 0.18-/spl mu/m CMOS and tested in a 10-cm test board achieves a data rate of 2 Gb/s/pin with multiple access and re-configurability between four (2-to-2) off-chip I/Os.

A wide-band 65nm CMOS 28–34 GHz synthesizer module enabling low power heterodyne spectrometers for planetary exploration

This paper presents a wide-band 28-34 GHz frequency synthesizer module developed to support THz spectrometer instruments for planetary exploration. The presented module features low power operation and a small form factor to be compatible with the demanding payload requirements of NASA planetary missions. The core of the module is a CMOS System-on-Chip (SoC) containing a sub-sampled phase-detector (SSPD) based phase lock-loop, power amplifier, power sensor and digital calibration. The demonstrated module draws a total of 81.2 mW of power from a USB connection and provides coverage from 28-34 GHz with output powers better than -4.0 dBm across the entire band. The offered mid-band phase noise is measured at -96.6 dBc/Hz evaluated at 1 MHz offset from the carrier.

Stream arbitration: Towards efficient bandwidth utilization for emerging on-chip interconnects

Alternative interconnects are attractive for scaling on-chip communication bandwidth in a power-efficient manner. However, efficient utilization of the bandwidth provided by these emerging interconnects still remains an open problem due to the spatial and temporal communication heterogeneity. In this article, a Stream Arbitration scheme is proposed, where at runtime any source can compete for any communication channel of the interconnect to talk to any destination. We apply stream arbitration to radio frequency interconnect (RF-I). Experimental results show that compared to the representative token arbitration scheme, stream arbitration can provide an average 20% performance improvement and 12% power reduction.

RF-interconnect for multi-Gb/s digital interface based on 10 GHz RF-modulation in 0.18 /spl mu/m CMOS

Presents an RF-interconnect (RFI) for multi-Gb/s digital interface based on capacitive coupling and RF-modulation over an impedance-matched transmission line. The RFI can reduce the switching noise coupling greatly and eliminate the dc current dissipation completely over the channel. The improved signal-to-noise ratio enables data transmission with reduced signal swing (as low as 0.2 V) and potentially enhanced data speed. A prototype RFI implemented in 0.18 /spl mu/m CMOS demonstrates a maximum data rate of 2.2 Gb/s with 10.5 GHz RF-carrier.

A 2.2 GS/s 188mW spectrometer processor in 65nm CMOS for supporting low-power THz planetary instruments

The paper presents a 2.2 GS/s (1.1 GHz Nyquist bandwidth), 188 mW 512-channel spectrometer processor developed to support of future science observations on NASA planetary missions, where payload size, weight, and power consumption are extremely limited. The presented spectrometer processor chip contains a pair of 7 bit ADC IQ converters coupled with a 512 point PSD processor, and averaging accumulator, allowing it to be sensitive enough to detect trace gases like NH3, HCN, and CO2 when coupled to the appropriate band RF front-end receiver. The bandwidth and resolution of the presented processor make it suitable for exploring the composition of planets, moons and their atmospheres throughout our solar system.

Evaluation of 28 nm CMOS Receivers at 183 GHz for Space-borne Atmospheric Remote Sensing

This letter discusses the capability of 28 nm CMOS technology to implement receivers at the 183 GHz band enabling the potential of future radiometers for monitoring atmospheric water vapor. To demonstrate the potential of 28 nm for constructing receivers at these frequencies, a prototype LNA and downconverter chip is demonstrated and measurements of both gain and noise performance are presented. The prototype receiver consumes 191 mW of DC power while providing noise temperatures on the order of 2700 K which demonstrates the potential for use in payload restricted cubesats and other small spacecraft platforms.

A W-Band 65nm CMOS/InP-hybrid radiometer & passive imager

This paper presents a 90-100 GHz heterodyne radiometer module based on a CMOS receiver system-on-chip (SoC). The SoC contains a frequency synthesizer, downconverter, RF&IF amplification, as well as a wide range of auto-leveling and calibration, and LO stabilization functions. To provide low-noise operation the CMOS SoC is packaged within a waveguide block and mated with an InP MMIC based LNA pre-amplifier. The complete module delivers noise performance below 400°K and is capable of less than 0.5K NEΔT with an integration time of 50 ms. The entire radiometer instrument consumes 257mW of power and weighs only 334 grams.