M. J. Hafich

Electrical and optical characteristics of AlAsSb/GaAsSb distributed Bragg reflectors for surface emitting lasers

We demonstrate an undoped 20 1/2 pair AlAsSb/GaAsSb distributed Bragg reflector (DBR) grown lattice matched to an InP substrate by molecular beam epitaxy. Reflectivity measurements indicate a stop band centered at 1.78 μm with a maximum reflectivity exceeding 99%. We also measure current–voltage characteristics in a similar 10 1/2 period p‐type DBR and find that a current density of 1 kA/cm2 produces a 2.5 V drop. Hole mobilities and doping concentrations in AlAsSb and GaAsSb are also reported.

Wet oxidation of AlxGa1−xAs: Temporal evolution of composition and microstructure and the implications for metal-insulator-semiconductor applications

Three important processes dominate the wet thermal oxidation of AlxGa1−xAs on GaAs: (1) oxidation of Al and Ga in the AlxGa1−xAs alloy to form an amorphous oxide, (2) formation and elimination of crystalline and amorphous elemental As and of amorphous As2O3, and (3) crystallization of the amorphous oxide film. Residual As can lead to strong Fermi-level pinning at the oxidized AlGaAs/GaAs interface, up to a 100-fold increase in leakage current, and a 30% increase in the dielectric constant of the oxide layer. Thermodynamically favored interfacial As may impose a fundamental limitation on the use of AlGaAs wet oxidation in metal-insulatorsemiconductor devices in the GaAs material system.

Wet thermal oxidation of AlAsSb lattice matched to InP for optoelectronic applications

We demonstrate wet thermal oxidation of an AlAsSb layer lattice matched to an InP substrate. Oxidation in an InGaAs/AlAsSb/InGaAs structure proceeds in a lateral direction, producing an oxide layer embedded between two layers of InGaAs. Auger analysis and Raman spectroscopy indicate conversion of the AlAsSb into an aluminum oxide with an elemental antimony layer at the top oxide‐InGaAs interface. Scanning electron microscope cross‐sectional views of partially and fully oxidized samples are also presented.

Planar quantum transistor based on 2D–2D tunneling in double quantum well heterostructures

We report on our work on the double electron layer tunneling transistor (DELTT), based on the gate-control of two-dimensional -- two-dimensional (2D-2D) tunneling in a double quantum well heterostructure. While previous quantum transistors have typically required tiny laterally-defined features, by contrast the DELTT is entirely planar and can be reliably fabricated in large numbers. We use a novel epoxy-bond-and-stop-etch (EBASE) flip-chip process, whereby submicron gating on opposite sides of semiconductor epitaxial layers as thin as 0.24 microns can be achieved. Because both electron layers in the DELTT are 2D, the resonant tunneling features are unusually sharp, and can be easily modulated with one or more surface gates. We demonstrate DELTTs with peak-to-valley ratios in the source-drain I-V curve of order 20:1 below 1 K. Both the height and position of the resonant current peak can be controlled by gate voltage over a wide range. DELTTs with larger subband energy offsets ({approximately} 21 meV) exhibit characteristics that are nearly as good at 77 K, in good agreement with our theoretical calculations. Using these devices, we also demonstrate bistable memories operating at 77 K. Finally, we briefly discuss the prospects for room temperature operation, increases in gain, and high-speed.

Microstructure of GaN layers grown on (001) GaAs by plasma assisted molecular-beam epitaxy

High resolution electron microscopy has been applied to characterize the structure of β-GaN epilayers grown on (001) GaAs substrates by plasma-assisted molecular-beam epitaxy. An rf plasma source was used to promote chemically active nitrogen. An exposure of the layer surface to the As flux during the growth of the first few monolayers was shown to result in remarkably flat GaN–GaAs interface. The best quality GaN layers were achieved by near-stoichiometric nucleation with optimal Ga-to-N ratio. Deviation from these nucleation conditions leads to interface roughening and formation of the wurtzite phase within the GaN layer. All the layers contained a high density of stacking faults near the interface which sharply decreases toward the surface. Stacking faults were anisotropically distributed within the GaN layer probably due to different properties of α compared to β dislocations in cubic GaN. The majority of stacking faults intersect the interface along lines parallel to the major flat of the GaAs wafer. The stacking faults are often associated with atomic steps at the GaN–GaAs interface.

High-speed, cascaded optical logic operations using programmable optical logic gate arrays

Programmable optical logic operations are demonstrated using arrays of nonlatching binary optical switches consisting of vertical-cavity surface-emitting lasers, p-i-n photodetectors and heterojunction bipolar transistors. Individual arrays can perform Boolean optical logic functions at 100 Mb/s using both optical and electrical logic inputs, while the routing and fan-out of the optical logic outputs can be controlled at the gate level. Cascaded optical logic operation is demonstrated using two programmable logic gate arrays.

UNIPOLAR COMPLEMENTARY CIRCUITS USING DOUBLE ELECTRON LAYER TUNNELING TRANSISTORS

We demonstrate unipolar complementary circuits consisting of a pair of resonant tunneling transistors based on the gate control of 2D-2D interlayer tunneling, where a single transistor - in addition to exhibiting a welldefined negative-differential-resistance can be operated with either positive or negative transconductance. Details of the device operation are analyzed in terms of the quantum capacitance effect and band-bending in a double quantum well structure, and show good agreement with experiment. Application of resonant tunneling complementary logic is discussed by demonstrating complementary static random access memory using two devices connected in series.

Metal-sulfur-based air-stable passivation of GaAs with very low surface-state densities

An air-stable electronic surface passivation for GaAs and other III–V compound semiconductors that employs sulfur and a suitable metal ion, e.g., Zn, and that is robust towards plasma dielectric deposition has been developed. Initial improvements in photoluminescence are twice that of S-only treatments and have been preserved for >11 months with SiOxNy dielectric encapsulation. Photoluminescence and x-ray photoelectron spectroscopies indicate that the passivation consists of two major components with one being stable for >2 years in air. This process improves heterojunction bipolar transistor current gain for both large and small area devices.

Broad-band light-emitting diode for 1.4-2.0 μm using variable-composition InGaAs quantum wells

We describe a novel broad-band light-emitting diode employing InGaAs quantum wells with different bandgaps. The device structures were grown by molecular-beam epitaxy on InP substrates and consist of three In/sub x/Ga/sub 1-x/As quantum wells (x=0.4, 0.53, and 0.66) imbedded in the p-doped region of an InAlAs p-n junction diode. Electrons injected into the p-region are captured into the wells and recombine with holes to produce radiation at the three bandgap wavelengths. Broad-band emission over a large wavelength range (1.4-2.0 /spl mu/m) is easily achieved with this approach. These novel solid-state sources have a variety of potential applications, for example, in miniature spectrometer and sensor systems.<<ETX>>

Double electron layer tunnelling transistor (DELTT)

We demonstrate the double electron layer tunnelling transistor (DELTT), based on the gate control of two-dimensional-two-dimensional tunnelling in a double quantum well. Unlike previously proposed resonant tunnelling transistors, the DELTT is entirely planar and can be easily fabricated in large numbers. At 1.5 K we demonstrate peak-to-background ratios of :1 in source-drain conductance versus gate voltage and peak-to-valley ratios of :1 in the source-drain current versus source-drain voltage. Using a single DELTT in series with a load resistor, we demonstrate low-power bistable memories at 1.5 K. We also demonstrate a unipolar complementary static RAM by connecting two DELTTs in series.