M. Jagadesh Kumar

Doping-Less Tunnel Field Effect Transistor: Design and Investigation

Using calibrated simulations, we report a detailed study of the doping-less tunnel field effect transistor (TFET) on a thin intrinsic silicon film using charge plasma concept. Without the need for any doping, the source and drain regions are formed using the charge plasma concept by choosing appropriate work functions for the source and drain metal electrodes. Our results show that the performance of the doping-less TFET is similar to that of a corresponding doped TFET. The doping-less TFET is expected to be free from problems associated with random dopant fluctuations. Furthermore, fabrication of doping-less TFET does not require a high-temperature doping/annealing processes and therefore cuts down the thermal budget, opening up possibilities for fabricating TFETs on single crystal silicon-on-glass substrates formed by wafer scale epitaxial transfer.

Impact of Strain on Drain Current and Threshold Voltage of Nanoscale Double Gate Tunnel Field Effect Transistor: Theoretical Investigation and Analysis

Tunnel field effect transistor (TFET) devices are attractive as they show good scalability and have very low leakage current. However they suffer from low on-current and high threshold voltage. In order to employ the TFET for circuit applications, these problems need to be tackled. In this paper, a novel lateral strained double-gate TFET (SDGTFET) is presented. Using device simulation, we show that the SDGTFET has a higher on-current, low leakage, low threshold voltage, excellent subthreshold slope, and good short channel effects and also meets important ITRS guidelines.

Compact Analytical Model of Dual Material Gate Tunneling Field-Effect Transistor Using Interband Tunneling and Channel Transport

In this paper, we have developed a 2-D analytical model for surface potential and drain current for a long channel dual material gate (DMG) silicon-on-insulator (SoI) tunneling field-effect transistor (TFET). This model includes the effect of drain voltage, gate metal work function, oxide thickness, and silicon film thickness, without assuming a fully depleted channel. The proposed model also includes the effect of charge accumulation at the interface of the two gates and the variation in the tunneling volume with the applied gate voltage. The accuracy of the model is tested using 2-D numerical simulations. In comparison with the conventional TFET, the proposed model predicts that a DMGTFET provides a higher ON-state current (ION), a better ON-state to OFF-state current (ION/IOFF) ratio, and a better subthreshold slope.

Controlling Ambipolar Current in Tunneling FETs Using Overlapping Gate-on-Drain

In this paper, we have demonstrated that overlapping the gate on the drain can suppress the ambipolar conduction, which is an inherent property of a tunnel field effect transistor (TFET). Unlike in the conventional TFET where the gate controls the tunneling barrier width at both source-channel and channel-drain interfaces for different polarity of gate voltage, overlapping the gate on the drain limits the gate to control only the tunneling barrier width at the source-channel interface irrespective of the polarity of the gate voltage. As a result, the proposed overlapping gate-on-drain TFET exhibits suppressed ambipolar conduction even when the drain doping is as high as 1 × 1019 cm-3.

Estimation and Compensation of Process-Induced Variations in Nanoscale Tunnel Field-Effect Transistors for Improved Reliability

Tunnel field-effect transistors (TFETs) have extremely low leakage current, exhibit excellent subthreshold swing, and are less susceptible to short-channel effects. However, TFETs do face certain special challenges, particularly with respect to the process-induced variations in the following: 1) the channel length and 2) the thickness of the silicon thin film and gate oxide. This paper, for the first time, studies the impact of the aforementioned process variations on the electrical characteristics of a double-gate tunnel field-effect transistor (DGTFET). Using 2-D device simulations, we propose the strained DGTFET as a possible solution for effectively compensating the process-induced variations in the on-current, threshold voltage, and subthreshold swing and improving the reliability of the DGTFET.

Compact Analytical Drain Current Model of Gate-All-Around Nanowire Tunneling FET

In this paper, we propose a 2-D analytical model for surface potential and drain current for a long channel p-type gate-all-around nanowire tunneling field effect transistor with a circular cross section. This model includes the effect of drain voltage, gate metal work function, oxide thickness, and radius of the silicon nanowire without assuming a fully depleted channel. The proposed model also includes the effect of the variation in the tunneling volume with the applied gate voltage. The model is tested using 3-D numerical simulations and is found to be accurate for all gate voltages except for subthreshold region.

Dielectric-Modulated Impact-Ionization MOS Transistor as a Label-Free Biosensor

In this letter, we propose a dielectric-modulated impact-ionization MOS (DIMOS) transistor-based sensor for application in label-free detection of biomolecules. Numerous reports exist on the experimental demonstration of nanogap-embedded field effect transistor-based biosensors, but an impact-ionization MOS (I-MOS)-based biosensor has not been reported previously. The concept of a dielectric-modulated I-MOS-based biosensor is presented in this letter based on technology computer-aided design simulation study. The results show a high sensitivity to the presence of biomolecules even at small channel lengths. In addition, a low variability of the sensitivity to the charges on the biomolecule is observed. The high sensitivity, dominance of dielectric-modulation effects, and operation at even small channel lengths make the DIMOS biosensor a promising alternative for CMOS-based sensor applications.

Investigation of the novel attributes of a single-halo double gate SOI MOSFET: 2D simulation study

The novel features of an asymmetric double gate single halo (DG-SH) doped SOI MOSFET are explored theoretically and compared with a conventional asymmetric DG SOI MOSFET. The two-dimensional numerical simulation studies demonstrate that the application of single halo to the double gate structure results in threshold voltage roll-up, reduced DIBL, high drain output resistance, kink free output characteristics and increase in the breakdown voltage when compared with a conventional DG structure. For the first time, we show that the presence of single halo on the source side results in a step function in the surface potential, which screens the source side of the structure from the drain voltage variations. This work illustrates the benefits of high performance DG-SH SOI MOS devices over conventional DG MOSFET and provides an incentive for further experimental exploration.

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In this brief, we propose a new extended-p+ stepped gate (ESG) thin-film silicon-on-insulator laterally double-diffused metal-oxide-semiconductor (LDMOS) with an extended-p+ region beneath the source and a stepped gate structure in the drift region of the LDMOS. The hole current generated due to impact ionization is now collected from an n+- p+ junction instead of an n+-p junction, thus delaying the parasitic bipolar junction transistor action. The stepped gate structure enhances RESURF in the drift region and minimizes the gate-drain capacitance. Based on 2-D simulation results, we show that the ESG LDMOS exhibits approximately 63% improvement in breakdown voltage, 38% improvement in on-resistance, 11% improvement in peak transconductance, 18% improvement in switching speed, and 63% reduction in gate-drain charge density compared with the conventional LDMOS with a field plate.

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In this paper, we have worked out a pseudo-2-D-analytical model for surface potential and drain current of a long channel p-type dual material gate gate all-around nanowire tunneling field-effect transistor. The model incorporates the effect of drain voltage, gate metal work functions, thickness of oxide, and silicon nanowire radius. The model does not assume a fully depleted channel. With the help of this model, we have demonstrated the accumulation of charge at the interface of the two gates. The accuracy of the model is tested using the 3-D device simulator Silvaco Atlas.