Sneh Saurabh

Impact of Strain on Drain Current and Threshold Voltage of Nanoscale Double Gate Tunnel Field Effect Transistor: Theoretical Investigation and Analysis

Tunnel field effect transistor (TFET) devices are attractive as they show good scalability and have very low leakage current. However they suffer from low on-current and high threshold voltage. In order to employ the TFET for circuit applications, these problems need to be tackled. In this paper, a novel lateral strained double-gate TFET (SDGTFET) is presented. Using device simulation, we show that the SDGTFET has a higher on-current, low leakage, low threshold voltage, excellent subthreshold slope, and good short channel effects and also meets important ITRS guidelines.

Estimation and Compensation of Process-Induced Variations in Nanoscale Tunnel Field-Effect Transistors for Improved Reliability

Tunnel field-effect transistors (TFETs) have extremely low leakage current, exhibit excellent subthreshold swing, and are less susceptible to short-channel effects. However, TFETs do face certain special challenges, particularly with respect to the process-induced variations in the following: 1) the channel length and 2) the thickness of the silicon thin film and gate oxide. This paper, for the first time, studies the impact of the aforementioned process variations on the electrical characteristics of a double-gate tunnel field-effect transistor (DGTFET). Using 2-D device simulations, we propose the strained DGTFET as a possible solution for effectively compensating the process-induced variations in the on-current, threshold voltage, and subthreshold swing and improving the reliability of the DGTFET.