Rajat Vishnoi

Compact Analytical Model of Dual Material Gate Tunneling Field-Effect Transistor Using Interband Tunneling and Channel Transport

In this paper, we have developed a 2-D analytical model for surface potential and drain current for a long channel dual material gate (DMG) silicon-on-insulator (SoI) tunneling field-effect transistor (TFET). This model includes the effect of drain voltage, gate metal work function, oxide thickness, and silicon film thickness, without assuming a fully depleted channel. The proposed model also includes the effect of charge accumulation at the interface of the two gates and the variation in the tunneling volume with the applied gate voltage. The accuracy of the model is tested using 2-D numerical simulations. In comparison with the conventional TFET, the proposed model predicts that a DMGTFET provides a higher ON-state current (ION), a better ON-state to OFF-state current (ION/IOFF) ratio, and a better subthreshold slope.

Compact Analytical Drain Current Model of Gate-All-Around Nanowire Tunneling FET

In this paper, we propose a 2-D analytical model for surface potential and drain current for a long channel p-type gate-all-around nanowire tunneling field effect transistor with a circular cross section. This model includes the effect of drain voltage, gate metal work function, oxide thickness, and radius of the silicon nanowire without assuming a fully depleted channel. The proposed model also includes the effect of the variation in the tunneling volume with the applied gate voltage. The model is tested using 3-D numerical simulations and is found to be accurate for all gate voltages except for subthreshold region.

A Pseudo-2-D-Analytical Model of Dual Material Gate All-Around Nanowire Tunneling FET

In this paper, we have worked out a pseudo-2-D-analytical model for surface potential and drain current of a long channel p-type dual material gate gate all-around nanowire tunneling field-effect transistor. The model incorporates the effect of drain voltage, gate metal work functions, thickness of oxide, and silicon nanowire radius. The model does not assume a fully depleted channel. With the help of this model, we have demonstrated the accumulation of charge at the interface of the two gates. The accuracy of the model is tested using the 3-D device simulator Silvaco Atlas.

2-D Analytical Model for the Threshold Voltage of a Tunneling FET With Localized Charges

In this paper, we have developed a 2-D analytical model for the surface potential and threshold voltage of a tunneling field-effect transistor (TFET) with localized charges in the oxide. These charges are generated in the oxide due to hot carrier effects in the channel. The models are derived by dividing the channel into damaged and undamaged regions and then solving the 2-D Poissons equation in these regions. The threshold voltage is then extracted by using constant current method. The proposed models are verified by using 2-D device simulations. The model can be used to study the impact of localized charges on the threshold voltage of a TFET for varying device dimensions and charge densities and can also be utilized to design TFET-based charge trapped memory devices.

An Accurate Compact Analytical Model for the Drain Current of a TFET From Subthreshold to Strong Inversion

In this paper, we have developed a compact analytical model for the drain current of a silicon-on-insulator tunneling field-effect transistor. The model includes the effects of oxide thickness, body doping, drain voltage, and gate metal work function. The model calculates the drain current using a tangent line approximation method to integrate the tunneling generation rate in the source-body depletion region. The accuracy of the model is tested against 2-D numerical simulations. The model predicts the drain current accurately in both the ON state (strong inversion) as well as in the subthreshold region.

A Compact Analytical Model for the Drain Current of Gate-All-Around Nanowire Tunnel FET Accurate From Sub-Threshold to ON-State

We present a compact analytical model for the drain current of a gate-all-around nanowire tunneling field effect transistor. The model takes into account the effect of oxide thickness, body doping, drain voltage, and gate metal work function. The model uses a tangent line approximation method to integrate the tunneling generation rate in the source-body depletion region. The accuracy of the model is tested against three dimensional numerical simulations calibrated using experimental results. The model predicts the drain current accurately in both the on-state (strong inversion), as well as in the sub-threshold region.

DC Drain Current Model for Tunnel FETs Considering Source and Drain Depletion Regions

This paper presents a 2-D model for the DC drain current of a tunnelling field-effect transistor (TFET) considering the source and the drain depletion regions. Analytical expressions are derived for the surface potential, electric field and the band to band generation rate. The drain current is obtained by numerically integrating the generation rate across the entire device. The model is able to predict the ambipolar current as well as the effects of drain voltage in the saturation region. The model uses a semi-empirical approach to capture the transition between the linear and the saturation regions, which gives an infinitely differentiable transfer characteristics. This model includes the effects of drain voltage, gate metal work function, oxide thickness, and silicon film thickness. The accuracy of the model is confirmed by a comparison with 2-D numerical simulations. It is also demonstrated that the proposed model is scalable down to a channel length of 20 nm.

Two dimensional analytical model for the threshold voltage of a Gate All Around Nanowire tunneling FET with localized charges

In this paper, we have studied the effect of localized charges on the threshold voltage of a Gate All Around Nanowire TFET and a two dimensional (2D) analytical model is developed for studying these effects. These localized charges are generated in the oxide due to hot carrier effects (HCEs) arising due to high electric fields in the tunneling region of a TFET. The models are derived by dividing the channel into damaged and undamaged regions and then solving for the surface potential using the 2D Poissons equation in these regions. The threshold voltage is then extracted by using the constant current method. The models proposed are verified with 2D numerical simulations. The model can be used for varying device dimensions and charge densities and can also be utilized to design TFET based charge trapped memory devices.

A Compact Analytical Model for the drain current of a TFET with non-abrupt doping profile incorporating the effect of band-gap narrowing

In this paper, we have developed a compact analytical model for the drain current of a Silicon-on-Insulator (SOI) Tunneling Field Effect Transistor (TFET) with a non-abrupt lateral doping profile at the source-channel junction. The model highlights the effect of band gap narrowing in determining the drain current for a TFET with a non-abrupt doping profile. The model calculates the drain current by using a triangle approximation method to integrate the tunneling generation rate in the source-channel depletion region. The accuracy of the model is tested against two dimensional numerical simulations. The model predicts the drain current accurately in both the ON-state (strong inversion) as well as in the sub-threshold region.