M.M. De Souza

Investigating the stability of zinc oxide thin film transistors.

The stability of thin film transistors incorporating sputtered ZnO as the channel layer is investigated under gate bias stress. Positive stress results in a positive shift of the transfer characteristics, while negative stress results in a negative shift. Low bias stress has no effect on the subthreshold characteristics. This instability is believed to be a consequence of charge trapping at/near the channel/insulator interface. Higher biases and longer stress times cause degradation of the subthreshold slope, which is thought to arise as a consequence of defect state creation within the ZnO channel material. After all stress measurements, the devices recover their original characteristics at room temperature without any annealing.

Junctionless Multiple-Gate Transistors for Analog Applications

This paper presents the evaluation of the analog properties of nMOS junctionless (JL) multigate transistors, comparing their performance with those exhibited by inversion-mode (IM) trigate devices of similar dimensions. The study has been performed for devices operating in saturation as single-transistor amplifiers, and we have considered the dependence of the analog properties on fin width Wfin and temperature T. Furthermore, this paper aims at providing a physical insight into the analog parameters of JL transistors. For that, in addition to device characterization, 3-D device simulations were performed. It is shown that, depending on gate voltage, JL devices can present both larger Early voltage VEA and larger intrinsic voltage gain AV than IM devices of similar dimensions. In addition, VEA and AV are always improved in JL devices when the temperature is increased, whereas they present a maximum value around room temperature for IM transistors.

A low temperature combination method for the production of ZnO nanowires

The growth of large-area, patterned and oriented ZnO nanowires on silicon using a low temperature silicon-CMOS compatible process is demonstrated. Nanowire synthesis takes place using a thin nucleation layer of ZnO deposited by radiofrequency magnetron sputtering, followed by a hydrothermal growth step. No metal catalysts are used in the growth process. The ZnO nanowires have a wurtzite structure, grow along the c-axis direction and are distributed on the silicon substrate according to the pre-patterned nucleation layer. Room temperature PL measurements of the as-grown nanowires exhibit strong yellow-red emission under 325 nm excitation that is replaced by ultraviolet emission after annealing. This method can be used to integrate patterned 1D nanostructures in optoelectronic and sensing applications on standard silicon CMOS wafers.

A Comparison of the Performance and Stability of ZnO-TFTs With Silicon Dioxide and Nitride as Gate Insulators

The performance and stability of thin-film transistors with zinc oxide as the channel layer are investigated using gate bias stress. It is found that the effective channel mobility, ON/OFF ratio, and subthreshold slope of the devices that incorporate SiN are superior to those with SiO2 as the dielectric. The application of positive and negative stress results in the device transfer characteristics shifting in positive and negative directions, respectively. The devices also demonstrate a logarithmic time-dependent threshold voltage shift suggestive of charge trapping within the band gap and the band tails responsible for the deterioration of device parameters. It is postulated that this device instability is partly a consequence of the lattice mismatch at the channel/insulator interface. All stressed devices recover to near-original characteristics after a short period at room temperature without the need for any thermal or bias annealing.

Surface intercalation of gold underneath a graphene monolayer on SiC(0001) studied by scanning tunneling microscopy and spectroscopy

The effects of gold deposition on monolayer graphene (MG) epitaxied on SiC (0001) substrate are examined via scanning tunneling microscopy and scanning tunneling spectroscopy (STS). Two types of surfaces with distinctive topography are demonstrated: (i) intercalated gold clusters having no interaction with graphene and (ii) 13×13-G reconstruction attributed to a Moire pattern arising from the intercalation of 1 ML of gold between a MG and the underlying SiC substrate. This surface also displays a 23×23R30-Au (111) surface reconstruction interpreted as surface corrugation. The STS curve shows a possible hole-doping effect in the latter case.

Errata to “Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors”

This paper proposes a drain current model for triple-gate n-type junctionless nanowire transistors. The model is based on the solution of the Poisson equation. First, the 2-D Poisson equation is used to obtain the effective surface potential for long-channel devices, which is used to calculate the charge density along the channel and the drain current. The solution of the 3-D Laplace equation is added to the 2-D model in order to account for the short-channel effects. The proposed model is validated using 3-D TCAD simulations where the drain current and its derivatives, the potential, and the charge density have been compared, showing a good agreement for all parameters. Experimental data of short-channel devices down to 30 nm at different temperatures have been also used to validate the model.

Properties of light emitting organic materials within the context of future electrically pumped lasers

The quest for electrically pumped organic laser is now conducted in several places around the globe. In this paper we outline our approach to this long-term project and aim to describe both encouraging and challenging (discouraging?) results. We describe experimental results using polymers, polymer blends and triplet emitters in an LED configuration using either CW or pulsed mode of operation. We also describe results of modeling such structures with the aim of being able to design electrical and optical characteristics of future laser structures. Finally we describe an approach to modify material parameters so as to provide a range of building blocks for optoelectronic devices.

A high performance RF LDMOSFET in thin film SOI technology with step drift profile

A radio frequency (RF) LDMOSFET with step drift doping profile on a conventional thin film SOI substrate used for mainstream VLSI technology is evaluated. Detailed simulation indicates that step drift doping can enable increase in the breakdown voltage by as much as 21% in comparison to the conventional uniformly doped drift (UD) LDMOS. In the on-state the kink present in the I–V characteristic of the UD device is eliminated. The other improvements over the UD counterpart include improved on-state breakdown performance, reduced parasitic feedback capacitance, lower on-resistance, improved drain current saturation behaviour and reduced self-heating at bias point.

Lattice effects and entropy release at the low-temperature phase transition in the spin-liquid candidate kappa-(BEDT-TTF)2Cu2(CN)3.

The spin-liquid candidate kappa-(BEDT-TTF)2Cu2(CN)3 has been studied by measuring the uniaxial expansion coefficients alpha(i), the specific heat, and magnetic susceptibility. Special emphasis was placed on the mysterious anomaly around 6 K--a potential spin-liquid instability. Distinct and strongly anisotropic lattice effects have been observed at 6 K, clearly identifying this feature as a second-order phase transition. Owing to the large anomalies in alpha(i), the application of Grüneisen scaling has enabled us to determine the corresponding specific heat contribution and the entropy release. Comparison of the latter with available spin models suggests that spin degrees of freedom alone cannot account for the phase transition. Scenarios involving charge degrees of freedom are discussed.

Cryogenic Operation of Junctionless Nanowire Transistors

This letter presents the properties of nMOS junctionless nanowire transistors (JNTs) under cryogenic operation. Experimental results of drain current, subthreshold slope, maximum transconductance at low electric field, and threshold voltage, as well as its variation with temperature, are presented. Unlike in classical devices, the drain current of JNTs decreases when temperature is lowered, although the maximum transconductance increases when the temperature is lowered down to 125 K. An analytical model for the threshold voltage is proposed to explain the influence of nanowire width and doping concentration on its variation with temperature. It is shown that the wider the nanowire or the lower the doping concentration, the higher the threshold voltage variation with temperature.