M. Moralis-Pegios

Single Mode Optical Interconnects for future data centers

Towards Single Mode Fiber (SMF) based optical connections in Data Centers (DCs) we are presenting the SM platform of the EU FP7 project PhoxTror. The major building blocks envisioned in this area are a 3D transceiver with a capacity of up to 480 Gb/s and a 3D router with 480 Gb/s throughput based on a Si photonics switching matrix. Towards this goal it is presented the basic 2×2 switching elements, the 4×4 switching matrix of the router and the Optical Through Silicon Vias (OTSVs) that enable the 3D functionality in the Si interposer.

On-Chip SOI Delay Line Bank for Optical Buffers and Time Slot Interchangers

We demonstrate integrated silicon-on-insulator (SOI) spiral waveguides with record-high 2.6-ns/mm2 on-chip delay efficiency performing as delay bank stage in variable optical delay buffering and time-slot interchanger applications with 10-Gb/s optical packets. The micro-scale SOI chip comprises three integrated waveguide delay elements of different lengths, providing variable delays of 6.5, 11.3, and 17.2 ns, respectively. Utilizing two semiconductor optical amplifier Mach-Zehnder interferometer wavelength converters and on-chip packet delay, error-free on-chip variable delay buffering from 6.5 to 17.2 ns and successful time-slot interchanging for 10-Gb/s optical packets are presented.

A programmable Si-photonic node for SDN-enabled Bloom filter forwarding in disaggregated data centers

Programmable switching nodes supporting Software-Defined Networking (SDN) over optical interconnecting technologies arise as a key enabling technology for future disaggregated Data Center (DC) environments. The SDNenabling roadmap of intra-DC optical solutions is already a reality for rack-to-rack interconnects, with recent research reporting on interesting applications of programmable silicon photonic switching fabrics addressing board-to-board and even on-board applications. In this perspective, simplified information addressing schemes like Bloom filter (BF)-based labels emerge as a highly promising solution for ensuring rapid switch reconfiguration, following quickly the changes enforced in network size, network topology or even in content location. The benefits of BF-based forwarding have been so far successfully demonstrated in the Information-Centric Network (ICN) paradigm, while theoretical studies have also revealed the energy consumption and speed advantages when applied in DCs. In this paper we present for the first time a programmable 4x4 Silicon Photonic switch that supports SDN through the use of BF-labeled router ports. Our scheme significantly simplifies packet forwarding as it negates the need for large forwarding tables, allowing for its remote control through modifications in the assigned BF labels. We demonstrate 1x4 switch operation controlling the Si-Pho switch by a Stratix V FPGA module, which is responsible for processing the packet ID and correlating its destination with the appropriate BF-labeled outgoing port. DAC- and amplifier-less control of the carrier-injection Si-Pho switches is demonstrated, revealing successful switching of 10Gb/s data packets with BF-based forwarding information changes taking place at a time-scale that equals the duration of four consecutive packets.

A low-latency optical switch architecture using integrated um SOI-based contention resolution and switching

The urgent need for high-bandwidth and high-port connectivity in Data Centers has boosted the deployment of optoelectronic packet switches towards bringing high data-rate optics closer to the ASIC, realizing optical transceiver functions directly at the ASIC package for high-rate, low-energy and low-latency interconnects. Even though optics can offer a broad range of low-energy integrated switch fabrics for replacing electronic switches and seamlessly interface with the optical I/Os, the use of energy- and latency-consuming electronic SerDes continues to be a necessity, mainly dictated by the absence of integrated and reliable optical buffering solutions. SerDes undertakes the role of optimally synergizing the lower-speed electronic buffers with the incoming and outgoing optical streams, suggesting that a SerDes-released chip-scale optical switch fabric can be only realized in case all necessary functions including contention resolution and switching can be implemented on a common photonic integration platform. In this paper, we demonstrate experimentally a hybrid Broadcast-and-Select (BS) / wavelength routed optical switch that performs both the optical buffering and switching functions with μm-scale Silicon-integrated building blocks. Optical buffering is carried out in a silicon-integrated variable delay line bank with a record-high on-chip delay/footprint efficiency of 2.6ns/mm2 and up to 17.2 nsec delay capability, while switching is executed via a BS design and a silicon-integrated echelle grating, assisted by SOA-MZI wavelength conversion stages and controlled by a FPGA header processing module. The switch has been experimentally validated in a 3x3 arrangement with 10Gb/s NRZ optical data packets, demonstrating error-free switching operation with a power penalty of <5dB.

A low-latency high-port count optical switch with optical delay line buffering for disaggregated data centers (Invited)

Disaggregated Data Centers (DCs) have emerged as a powerful architectural framework towards increasing resource utilization and system power efficiency, requiring, however, a networking infrastructure that can ensure low-latency and high-bandwidth connectivity between a high-number of interconnected nodes. This reality has been the driving force towards high-port count and low-latency optical switching platforms, with recent efforts concluding that the use of distributed control architectures as offered by Broadcast-and-Select (BS) layouts can lead to sub-μsec latencies. However, almost all high-port count optical switch designs proposed so far rely either on electronic buffering and associated SerDes circuitry for resolving contention or on buffer-less designs with packet drop and re-transmit procedures, unavoidably increasing latency or limiting throughput. In this article, we demonstrate a 256x256 optical switch architecture for disaggregated DCs that employs small-size optical delay line buffering in a distributed control scheme, exploiting FPGA-based header processing over a hybrid BS/Wavelength routing topology that is implemented by a 16x16 BS design and a 16x16 AWGR. Simulation-based performance analysis reveals that even the use of a 2- packet optical buffer can yield <620nsec latency with >85% throughput for up to 100% loads. The switch has been experimentally validated with 10Gb/s optical data packets using 1:16 optical splitting and a SOA-MZI wavelength converter (WC) along with fiber delay lines for the 2-packet buffer implementation at every BS outgoing port, followed by an additional SOA-MZI tunable WC and the 16x16 AWGR. Error-free performance in all different switch input/output combinations has been obtained with a power penalty of <2.5dB.

Optical time-slot interchanger and Si-based delay lines towards integrated feed-forward buffers

We demonstrate a time-slot interchanger (TSI) unit utilizing differentially biased SOA-MZI wavelength converters. Replacement of the fiber delay lines with integrated waveguides is also investigated. We report error-free rearrangement of three 10Gbps data packets for the fiber case and error-free transmission through the integrated delays.