N. Terzenidis

On-Chip SOI Delay Line Bank for Optical Buffers and Time Slot Interchangers

We demonstrate integrated silicon-on-insulator (SOI) spiral waveguides with record-high 2.6-ns/mm2 on-chip delay efficiency performing as delay bank stage in variable optical delay buffering and time-slot interchanger applications with 10-Gb/s optical packets. The micro-scale SOI chip comprises three integrated waveguide delay elements of different lengths, providing variable delays of 6.5, 11.3, and 17.2 ns, respectively. Utilizing two semiconductor optical amplifier Mach-Zehnder interferometer wavelength converters and on-chip packet delay, error-free on-chip variable delay buffering from 6.5 to 17.2 ns and successful time-slot interchanging for 10-Gb/s optical packets are presented.

A programmable Si-photonic node for SDN-enabled Bloom filter forwarding in disaggregated data centers

Programmable switching nodes supporting Software-Defined Networking (SDN) over optical interconnecting technologies arise as a key enabling technology for future disaggregated Data Center (DC) environments. The SDNenabling roadmap of intra-DC optical solutions is already a reality for rack-to-rack interconnects, with recent research reporting on interesting applications of programmable silicon photonic switching fabrics addressing board-to-board and even on-board applications. In this perspective, simplified information addressing schemes like Bloom filter (BF)-based labels emerge as a highly promising solution for ensuring rapid switch reconfiguration, following quickly the changes enforced in network size, network topology or even in content location. The benefits of BF-based forwarding have been so far successfully demonstrated in the Information-Centric Network (ICN) paradigm, while theoretical studies have also revealed the energy consumption and speed advantages when applied in DCs. In this paper we present for the first time a programmable 4x4 Silicon Photonic switch that supports SDN through the use of BF-labeled router ports. Our scheme significantly simplifies packet forwarding as it negates the need for large forwarding tables, allowing for its remote control through modifications in the assigned BF labels. We demonstrate 1x4 switch operation controlling the Si-Pho switch by a Stratix V FPGA module, which is responsible for processing the packet ID and correlating its destination with the appropriate BF-labeled outgoing port. DAC- and amplifier-less control of the carrier-injection Si-Pho switches is demonstrated, revealing successful switching of 10Gb/s data packets with BF-based forwarding information changes taking place at a time-scale that equals the duration of four consecutive packets.

A low-latency optical switch architecture using integrated um SOI-based contention resolution and switching

The urgent need for high-bandwidth and high-port connectivity in Data Centers has boosted the deployment of optoelectronic packet switches towards bringing high data-rate optics closer to the ASIC, realizing optical transceiver functions directly at the ASIC package for high-rate, low-energy and low-latency interconnects. Even though optics can offer a broad range of low-energy integrated switch fabrics for replacing electronic switches and seamlessly interface with the optical I/Os, the use of energy- and latency-consuming electronic SerDes continues to be a necessity, mainly dictated by the absence of integrated and reliable optical buffering solutions. SerDes undertakes the role of optimally synergizing the lower-speed electronic buffers with the incoming and outgoing optical streams, suggesting that a SerDes-released chip-scale optical switch fabric can be only realized in case all necessary functions including contention resolution and switching can be implemented on a common photonic integration platform. In this paper, we demonstrate experimentally a hybrid Broadcast-and-Select (BS) / wavelength routed optical switch that performs both the optical buffering and switching functions with μm-scale Silicon-integrated building blocks. Optical buffering is carried out in a silicon-integrated variable delay line bank with a record-high on-chip delay/footprint efficiency of 2.6ns/mm2 and up to 17.2 nsec delay capability, while switching is executed via a BS design and a silicon-integrated echelle grating, assisted by SOA-MZI wavelength conversion stages and controlled by a FPGA header processing module. The switch has been experimentally validated in a 3x3 arrangement with 10Gb/s NRZ optical data packets, demonstrating error-free switching operation with a power penalty of <5dB.

A low-latency high-port count optical switch with optical delay line buffering for disaggregated data centers (Invited)

Disaggregated Data Centers (DCs) have emerged as a powerful architectural framework towards increasing resource utilization and system power efficiency, requiring, however, a networking infrastructure that can ensure low-latency and high-bandwidth connectivity between a high-number of interconnected nodes. This reality has been the driving force towards high-port count and low-latency optical switching platforms, with recent efforts concluding that the use of distributed control architectures as offered by Broadcast-and-Select (BS) layouts can lead to sub-μsec latencies. However, almost all high-port count optical switch designs proposed so far rely either on electronic buffering and associated SerDes circuitry for resolving contention or on buffer-less designs with packet drop and re-transmit procedures, unavoidably increasing latency or limiting throughput. In this article, we demonstrate a 256x256 optical switch architecture for disaggregated DCs that employs small-size optical delay line buffering in a distributed control scheme, exploiting FPGA-based header processing over a hybrid BS/Wavelength routing topology that is implemented by a 16x16 BS design and a 16x16 AWGR. Simulation-based performance analysis reveals that even the use of a 2- packet optical buffer can yield <620nsec latency with >85% throughput for up to 100% loads. The switch has been experimentally validated with 10Gb/s optical data packets using 1:16 optical splitting and a SOA-MZI wavelength converter (WC) along with fiber delay lines for the 2-packet buffer implementation at every BS outgoing port, followed by an additional SOA-MZI tunable WC and the 16x16 AWGR. Error-free performance in all different switch input/output combinations has been obtained with a power penalty of <2.5dB.

Harnessing path diversity for laser control in data center optical networks

Optical interconnects are already the dominant technology in large-scale datacenter networks. Unfortunately, the high optical loss of many optical components, coupled with the low efficiency of laser sources, result in high aggregate power requirements for the thousands of optical transceivers that such networks employ. As optical interconnects stay always on, even during periods of system inactivity, most of this power is wasted. Ideally we would like to turn off the transceivers when a network link is idle (i.e., “power gate” the lasers), and turn them back on right before the next transmission. The danger with this approach is that it may expose the laser turn-on delay and lead to higher network latency. However, data center networks typically employ network topologies with path diversity and facilitate multiple paths for each source-destination pair. Based on this observation, we propose an optical network architecture where redundant paths are turned off when the extra bandwidth they provide is not needed, and they turn back on when traffic increases beyond a high watermark to decongest the network. Maintaining full connectivity removes the laser turn-on latency from the critical path and results in minimal performance degradation, while at the same time power-gating the lasers saves 60% of the laser power on average on a variety of data center traffic scenarios.

Optical interconnect and memory components for disaggregated computing

High-performance server boards rely on multi-socket architectures for increasing the processing power density on the board level and for flattening the data center networks beyond leaf-spine architectures. Scaling, however, the number of processors per board and retaining at the same time low-latency and high-throughput metrics puts current electronic technologies into challenge. In this article, we report on our recent work carried out in the H2020 projects ICT-STREAMS and dREDBox that promotes the use of Silicon Photonic transceiver and routing modules in a powerful board-level, chip-to-chip interconnect paradigm. The proposed on-board platform leverages WDM parallel transmission with a powerful wavelength routing approach that is capable of interconnecting multiple processors with up to 25.6 Tbps on-board throughput, providing direct and collision-less any-to-any communication between multiple compute and memory sockets at low-energy 50 Gbps OOK line-rates. We demonstrate recent advances on the Si-based WDM transceiver, cyclic AWGR router and polymer-based electro-optical circuit board key-enabling technologies, discussing also potential applications in disaggregated rack-scale architectures. We also demonstrate our recent research on optical RAM technologies and optical cache memory architectures that can take advantage of the on-board interconnect technology for yielding true disintegrated computing resolving both power and memory bandwidth bottlenecks of current computational settings.

Software-defined board- and chip-level optical interconnects for multi-socket communication and disaggregated computing

The vast amount of new data being generated is outpacing the development of infrastructures and continues to grow at much higher rates than MooreâĂŹs law, a problem that is commonly referred to as the âĂIJdata deluge problemâĂİ. This brings current computational machines in the struggle to exceed Exascale processing powers by 2020 and this is where the energy boundary is setting the second, bottom-side alarm: A reasonable power envelope for future Super-computers has been projected to be 20MW, while worldâĂŹs current No. 1 Supercomputer Sunway TaihuLight provides 93 Pflops and requires already 15.37 MW. This simply means that we have reached so far below 10% of the Exascale target but we consume already more than 75% of the tar-geted energy limit! The way to escape is currently following the paradigm of disaggregating and disintegrating resources, massively introducing at the same time optical technologies for interconnect purposes. Disaggregating computing from memory and storage modules can allow for flexible and modular settings where hardware requirements can be tailored to meet the certain energy and performance metrics targeted per application. At the same time, optical interconnect and photonic integration technologies are rapidly replacing electrical interconnects continuously penetrating at deeper hierarchy levels: Silicon photonics have enabled the penetration of optical technology to the computing environment, starting from rack-to-rack and gradually shifting towards board-level communications. In this article, we present our recent work towards implementing on-board single-mode optical interconnects that can support Software Defined Networking allowing for programmable and flexible computational settings that can quickly adapt to the application requirements. We present a programmable 4×4 Silicon Photonic switch that supports SDN through the use of Bloom filter (BF) labeled router ports. Our scheme significantly simplifies packet forwarding as it negates the need for large forwarding tables, supporting at the same time network size and topol-ogy changes through simple modifications in the assigned BF labels. We demonstrate 1×4 switch operation controlling the Si-Pho switch by a Stratix V FPGA board that is responsible for processing the packet ID and correlating its destination with the appropriate BF-labeled switch output port. Moving towards high-capacity board-level settings, we discuss the architecture and technology being currently promoted by the recently started H2020 project ICT-STREAMS, where single-mode optical PCBs hosting Si-based routing modules and mid-board transceiver optics expect to enable a massive any-to-any, buffer-less, collision-less and extremely low latency routing platform with 25.6Tb/s aggregate through-put. This architecture and technology are also extended to support resource disaggregation in data centers as currently being pursued in the H2020 project dREDBox, where the any-to-any collisionless routing scheme is proposed for connecting disaggregated computing and memory bricks trying to minimize remote memory access latency and energy consumption.