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Dive into the research topics where M. Nagase is active.

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Featured researches published by M. Nagase.


Microelectronic Engineering | 1998

Nano-patterning of a hydrogen silsesquioxane resist with reduced linewidth fluctuations

Hideo Namatsu; T. Yamaguchi; M. Nagase; Kenji Yamazaki; Kenji Kurihara

Abstract A new resist system providing small linewidth fluctuation has been developed for nanolithography. Hydrogen silsesquioxane (HSQ) resist used here has a small polymer size because of its three-dimensional framework. This framework reduces the size of aggregates in the resist film which strongly influence linewidth fluctuation of resist patterns. The scission of SiH bonds in HSQ by e-beam leads to the crosslinking required for the nega-patterning. In addition, the application of a TMAH developer realizes higher contrast and less thickness loss. Consequently, 20-nm-wide nega-patterns with a rectangular cross-sectional shape are successfully formed with linewidth fluctuation less than 2 nm.


international microprocesses and nanotechnology conference | 2002

Line-edge roughness: characterization and material origin

Toru Yamaguchi; Kenji Yamazaki; M. Nagase; Hideo Namatsu

Among lithographic characteristics, line-edge roughness (LER) of resist patterns now assumes even greater importance than before. This is because the variation of device sizes due to LER cannot be neglected as device sizes shrink. Therefore, LER has to be reduced as much as possible in next-generation lithography. For LER reduction, it is essential to elucidate its cause based on precise evaluations. We have been working to develop methods for the measurement and analysis of LER and elucidate the cause of LER for an electron-beam chain-scission type of resist, which has a simple imaging mechanism. In this report, we describe two LER issues: its characterization and material origin.


Microelectronic Engineering | 1998

Si nanostructures formed by pattern-dependent oxidation

M. Nagase; Akira Fujiwara; Kenji Yamazaki; Yasuo Takahashi; Katsumi Murase; Kenji Kurihara

Abstract A quantitative evaluation of the local Si thickness of oxidized Si nanostructures was performed by scanning probe microscopy. Suppression of oxidation by mechanical stress is a dominant factor in determining the shape of Si structures of widths


Microelectronic Engineering | 1996

Nano-scale fluctuations in electron beam resist pattern evaluated by atomic force microscopy

M. Nagase; Hideo Namatsu; Kenji Kurihara; Kazumi Iwadate; Katsumi Murase; T. Makino

Abstract The resist pattern fluctuations on the nano-scale are successfully observed using a dynamic force mode AFM. A scaling analysis based on the fractals applies to the AFM images for quantitative evaluation of the fluctuations. The standard deviation of width fluctuations in a ZEP resist pattern is 2.8 nm. The scaling analysis confirms that the surface morphology of the pattern sidewall is almost the same as that of the resist film lightly exposed by an electron beam. The main cause of the fluctuation is structures with a diameter of 20–30 nm which are composed of large groups of molecules.


international electron devices meeting | 1999

Si complementary single-electron inverter

Yukinori Ono; Yasuo Takahashi; Kenji Yamazaki; M. Nagase; Hideo Namatsu; Kenji Kurihara; Katsumi Murase

A complementary single-electron inverter occupying an extremely small area is fabricated on an SOI substrate. For the fabrication, the vertical pattern-dependent oxidation method, which enables the formation of two tiny single-electron transistors (SETs) aligned in parallel, is advanced so that the two SETs are connected in series to realize an inverter configuration. By controlling peak positions of the conductance curve of the SETs in the inverter using the side gates situated near each SET, input-output transfer with a gain larger than unity is demonstrated at 27 K.


international electron devices meeting | 1994

Conductance oscillations of a Si single electron transistor at room temperature

Yasuo Takahashi; M. Nagase; Hideo Namatsu; Kenji Kurihara; K. Iwdate; Y. Nakajima; S. Horiguchi; Katsumi Murase; M. Tabe

The single electron transistor (SET) is a key element in single electronics where device operation is based on one-by-one electron manipulation utilizing the Coulomb blockade effect. However, SET operation has so far been limited to below 4 K because even the smallest capacitance C of the SET has been about 100 aF. This means the requirement of charging energy e/sup 2/(2C) being much larger than the thermal energy could only be met at very low temperatures. We report here a Si-SET whose capacitance is only about 2 aF. Owing to this small capacitance, the Si-SET shows conductance oscillation even at room temperature.<<ETX>>


Proceedings of SPIE, the International Society for Optical Engineering | 1999

Line-edge roughness characterized by polymer aggregates in photoresists

Toru Yamaguchi; Hideo Namatsu; M. Nagase; Kenji Kurihara; Yoshio Kawai

We investigate the origin of the line-edge roughness (LER) of line patterns of chemically amplified photo resist for the purpose of reducing size fluctuations of patterns in present and future deep-UV lithography. An atomic force microscope analysis of the pattern sidewall reveals that there are tow kinds of roughness in the LER: short-range roughness with an average period of about 50 nm and long- range roughness with an average period of about 500 nm. The short-range roughness can be identified as polymer aggregates, which are essentially formed by the base polymer in the resist film. This is because the average period of the surface roughness due to polymer aggregates observed in the base polymer films is about the same as that of the short-range roughness. In addition, it is confirmed that aggregate extraction development occurs in the photoresist. On the other hand, the long-range roughness is generated not by the base polymer only but also by the exposure process because its average period increases with the exposure dose. The origin of the long-range roughness is also discussed.


Microelectronic Engineering | 1995

10-nm silicon lines fabricated in (110) silicon

Hideo Namatsu; M. Nagase; Kenji Kurihara; Kazumi Iwadate; Katsumi Murase

A technique which satisfies both high resolution and minimum linewidth fluctuation has been developed for fabrication of nanometer-scale Si structures. The technique is based on the development of resist with hexyl acetate and the anisotropic etching of Si with KOH. The combination of ZEP-520 resist and hexyl acetate developer is effective to improve the resolution and reduce pattern fluctuation in e-beam lithography. Resist lines less than 20 nm wide with a fluctuation less than 3 nm are obtained. When these lines, aligned in the direction on a (110) Si wafer by using the fan-pattern method, are transferred to Si by KOH etching, linewidth fluctuation is reduced further because the (111) planes from the sidewalls. In addition, a feature size as small as 7 nm can be formed by additional etching using alcohol-added KOH solution.


Microelectronic Engineering | 1997

Room temperature operated single electron transistor fabricated by electron beam nanolithography

Kenji Kurihara; Hideo Namatsu; M. Nagase; T. Makino

Abstract We have fabricated a Si-based single electron transistor (SET) with precisely controlled structure using a newly developed electron beam nanolithography system and a Si nanofabrication process. A Si island and tunnel barriers are fabricated by trench etching with reactive ion etching on a superficial Si layer of SIMOX substrate, combined with an image reversal technique using ECR plasma oxidation. The SET fabricated with this method accommodates a 10-nm Si island and achieved room temperature operation.


Applied Surface Science | 2002

Single-electron devices formed by pattern-dependent oxidation: microscopic structural evaluation

M. Nagase; Seiji Horiguchi; Akira Fujiwara; Yukinori Ono; Kenji Yamazaki; Hideo Namatsu; Yasuo Takahashi

The embedded Si structure formed by pattern-dependent oxidation (PADOX) in single-electron device (SED) is analyzed by novel microscopic methods using scanning electron microscopy (SEM) and atomic force microscopy (AFM). The surface charge imaging SEM reveals the outline of the embedded Si nanowire of the electrically-measured SED. The size of the wire in the device is small enough to make a potential barrier caused by the quantum mechanical size effect. The result of the Si height in the oxidized structure estimated by AFM indicates that the huge stress induced by oxidation is applied to the narrow Si wire. The experimental results support the theoretical model of the SED fabricated by PADOX that the potential profile responsible for the SED operation is produced by two effects, the quantum mechanical size effect and the strain-induced bandgap reduction.

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Hideo Namatsu

Nippon Telegraph and Telephone

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Kenji Yamazaki

Nippon Telegraph and Telephone

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Akira Fujiwara

Nippon Telegraph and Telephone

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Toru Yamaguchi

Nippon Telegraph and Telephone

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H. Yamaguchi

Nippon Telegraph and Telephone

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K. Nonaka

Nippon Telegraph and Telephone

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