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Dive into the research topics where Hideo Namatsu is active.

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Featured researches published by Hideo Namatsu.


Journal of Vacuum Science & Technology B | 1998

Three-dimensional siloxane resist for the formation of nanopatterns with minimum linewidth fluctuations

Hideo Namatsu; Yasuo Takahashi; Kenji Yamazaki; Toru Yamaguchi; Masao Nagase; Kenji Kurihara

Linewidth fluctuation of resist patterns is a serious problem in fabricating nanodevices when lithographic resolution is improved to the nanometer scale. As a resist material for reducing linewidth fluctuations, we evaluate hydrogen silsesquioxane (HSQ) with a three-dimensional framework from the standpoints of resist patterning and its ability to reduce linewidth fluctuation. Infrared analyses indicate that SiH bonds in HSQ are broken by electron-beam irradiation, and consequently, the crosslinking required for negative tone patterning is generated. By applying a TMAH developer suitable for the dissolution of the siloxane bonds in HSQ, we improve contrast and reduce the thickness loss of the lightly exposed resist area. In addition, the HSQ resist has relatively high sensitivity for resist materials without any reactive groups. The etching durability sacrificed for the attainment of high sensitivity is improved by oxygen plasma treatment. No damage, such as pattern-shape deformation after the oxygen plas...


IEEE Transactions on Electron Devices | 1996

Size dependence of the characteristics of Si single-electron transistors on SIMOX substrates

Yasuo Takahashi; Hideo Namatsu; Kenji Kurihara; K. Iwadate; Masao Nagase; Katsumi Murase

A Si single-electron transistor (SET) was fabricated by converting a one-dimensional (1-D) Si wire on a SIMOX substrate into a small Si island with a tunneling barrier at each end by means of pattern-dependent oxidation. Since the size of the Si island became as small as around 10 nm owing to this novel technique, the total capacitance of the SET was reduced to a value of the order of 1 aF, which guaranteed the conductance oscillation of the SET even at room temperature. Furthermore, a linear relation between the designed wire length and the gate capacitance of SETs was obtained, which clearly indicates that the single island was actually formed in the middle of the one dimensional Si wire. These results were achieved owing to the highly reproducible fabrication process based on pattern dependent oxidation of SIMOX-Si layers.


Microelectronic Engineering | 1998

Nano-patterning of a hydrogen silsesquioxane resist with reduced linewidth fluctuations

Hideo Namatsu; T. Yamaguchi; M. Nagase; Kenji Yamazaki; Kenji Kurihara

Abstract A new resist system providing small linewidth fluctuation has been developed for nanolithography. Hydrogen silsesquioxane (HSQ) resist used here has a small polymer size because of its three-dimensional framework. This framework reduces the size of aggregates in the resist film which strongly influence linewidth fluctuation of resist patterns. The scission of SiH bonds in HSQ by e-beam leads to the crosslinking required for the nega-patterning. In addition, the application of a TMAH developer realizes higher contrast and less thickness loss. Consequently, 20-nm-wide nega-patterns with a rectangular cross-sectional shape are successfully formed with linewidth fluctuation less than 2 nm.


Journal of Vacuum Science & Technology B | 1998

Influence of edge roughness in resist patterns on etched patterns

Hideo Namatsu; Masao Nagase; Toru Yamaguchi; Kenji Yamazaki; Kenji Kurihara

We report on the linewidth fluctuations in resist patterns and their influence on etched patterns. The linewidth fluctuations observed as line edge roughness are mainly caused by polymer aggregates in the resist materials. Polymer aggregates more than 30 nm in diameter are observed in both the positive and negative resist films. Because the polymer aggregates are not dissolved but extracted during development, they remain stuck on the pattern sidewall and cause linewidth fluctuations. When substrates, such as Si, are etched using resist patterns as a mask, the linewidth fluctuations of the resist patterns are faithfully transferred to the substrate. This means that the linewidth fluctuations in device patterns are originally due to the polymer aggregates in the resist films. The linewidth fluctuation is also found to decrease through substrate etching, depending on resist thickness loss. This possibly results from degradation of the resist patterns in lateral directions through etching. However, it does n...


Applied Physics Letters | 1995

DIMENSIONAL LIMITATIONS OF SILICON NANOLINES RESULTING FROM PATTERN DISTORTION DUE TO SURFACE TENSION OF RINSE WATER

Hideo Namatsu; Kenji Kurihara; Masao Nagase; Kazumi Iwadate; Katsumi Murase

In a nanometer‐scale regime, high‐aspect‐ratio Si lines running in parallel bend plastically toward each other during the drying process after being rinsed in water. Pattern distortion occurs when the line distance is smaller than the product of the squared aspect ratio and a constant k dependent on the condition of the Si surface, i.e., (distance)<k×(aspect ratio)2. This relationship can be derived theoretically on the assumption that water remains between lines and the water pressure is reduced due to the surface tension of water.


IEEE Transactions on Electron Devices | 2000

Fabrication method for IC-oriented Si single-electron transistors

Yukinori Ono; Yasuo Takahashi; Kenji Yamazaki; Masao Nagase; Hideo Namatsu; Kenji Kurihara; Katsumi Murase

A new fabrication method for Si single-electron transistors (SETs) is proposed. The method applies thermal oxidation to a Si wire with a fine trench across it on a silicon-on-insulator substrate. During the oxidation, the Si wire with the fine trench is converted, in a self-organized manner, into a twin SET structure with two single-electron islands, one along each edge of the trench, due to position-dependent oxidation-rate modulation caused by stress accumulation. Test devices demonstrated, at 40 K, that the twin SET structure can operate as two individual SETs. Since the present method produces two SETs at the same time in a tiny area, it is suitable for integrating logic circuits based on pass-transistor type logic and CMOS-type logic, which promises to lead to the fabrication of single-electron logic LSIs.


Applied Physics Letters | 2006

Single electron tunneling transistor with tunable barriers using silicon nanowire metal-oxide-semiconductor field-effect transistor

Akira Fujiwara; Hiroshi Inokawa; Kenji Yamazaki; Hideo Namatsu; Yasuo Takahashi; Neil M. Zimmerman; Stuart Martin

We have achieved the operation of single-electron tunneling (SET) transistors with gate-induced electrostatic barriers using silicon nanowire metal-oxide-semiconductor field-effect transistor (MOSFET) structures. The conductance of tunnel barriers is tunable by more than three orders of magnitude. By using the flexible control of the tunable barriers, the systematic evolution from a single charge island to double islands was clearly observed. We obtained excellent reproducibility in the gate capacitances: values on the order of 10 aF, with the variation smaller than 1 aF. This flexibility and controllability both demonstrate that the device is highly designable to build a variety of SET devices based on complementary metal-oxide-semiconductor technology.


Applied Physics Letters | 1997

NANOMETER-SCALE LINEWIDTH FLUCTUATIONS CAUSED BY POLYMER AGGREGATES IN RESIST FILMS

Toru Yamaguchi; Hideo Namatsu; Masao Nagase; Kenji Yamazaki; Kenji Kurihara

Linewidth fluctuation in resist patterns is a serious problem in electron beam nanolithography. We have observed granular structures with a diameter of 20–30 nm in resist films, and have determined that these structures cause the linewidth fluctuations. The granules are made up of polymer aggregates. We discuss the origin of the aggregates from the result that their size depends on the polymer molecular weight. We also show that the linewidth fluctuation is reduced, though the developing rate is slow, when the pattern size is less than the aggregate size. The linewidth dependence of the fluctuation and of the developing rate can be explained by the influence of the resist polymer aggregate on the development behavior.


Applied Physics Letters | 2000

Multigate single-electron transistors and their application to an exclusive-OR gate

Yasuo Takahashi; Akira Fujiwara; Kenji Yamazaki; Hideo Namatsu; Kenji Kurihara; Katsumi Murase

The two-input exclusive-OR (XOR) function was implemented by a multigate single-electron transistor (SET). Two types of multigate SETs operating at 40 K were fabricated on a top silicon layer of an Si-on-insulator wafer by using a special technique called pattern-dependent oxidation. Two small gate electrodes which act as the input gates were formed over the small SET island. The output current of the devices took a high level when a high voltage was applied to either of the two gates with the other gate grounded, while it took a low level when both gates were grounded or fed with a high voltage. It is striking that such an XOR function can be implemented with just one device.


Applied Physics Letters | 2000

Si complementary single-electron inverter with voltage gain

Yukinori Ono; Yasuo Takahashi; Kenji Yamazaki; Masao Nagase; Hideo Namatsu; Kenji Kurihara; Katsumi Murase

A Si complementary single-electron inverter in which two identical single-electron transistors (SETs) are packed is fabricated on a silicon-on-insulator substrate. For the fabrication, the vertical pattern-dependent oxidation method, which enables the formation of two tiny SETs aligned in parallel, is modified so that the two SETs can be connected in series to realize an inverter configuration. The resultant circuit occupies a very small area: 100×100 nm for each SET. For complementary operation, the electrical characteristics of one of the SETs are shifted using a side gate situated near the SET. Input–output transfer with a voltage gain larger than unity is demonstrated at 27 K.

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Kenji Yamazaki

Nippon Telegraph and Telephone

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Masao Nagase

University of Tokushima

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Toru Yamaguchi

Nippon Telegraph and Telephone

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Akira Fujiwara

Nippon Telegraph and Telephone

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M. Nagase

Nippon Telegraph and Telephone

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