M. Nakamae

A 'self-aligned' selective MBE technology for high-performance bipolar transistors

A novel method of preparing high-performance self-aligned silicon bipolar transistors having a Si MBE (molecular beam epitaxy) base layer, called SSSB (super self-aligned selectively grown base) technology, has been developed. An SSSB technology features the simultaneous formation of a facet-free, ultrathin selective silicon epitaxial layer, and a selectively deposited graft base polysilicon film. Under an optimized gas-source MBE process condition, uniform epitaxial growth onto the

A 40 GHz f/sub T/ Si bipolar transistor LSI technology

A high-speed Si bipolar transistor with f/sub T/ (cutoff frequency) of 40 GHz using advanced BSA (BSG self-aligned) technology is described. The advanced BSA technology is characterized by graded profiled collector, buried emitter electrode structure, and 0.8- mu m design rule. The advanced BSA technology for further improving the f/sub T/ performance of the sub-100-nm-deep base transistor has been developed by adding these three technologies to the basic BSA technology, in which chemical vapor deposition (CVD)-BSG film is used as a diffusion source to form the intrinsic base and the p/sup +/-link region and as a sidewall spacer between emitter polysilicon and base polysilicon electrodes. The optimized transistor using the advanced BSA technology has exhibited a cutoff frequency of 38 GHz at V/sub CE/ of 1 V, and ECL (emitter coupled logic) gate delay time of 29 ps at I/sub CS/ of 0.3 mA.<<ETX>>

BSA Technology for sub-100nm deep base bipolar transistors

This paper will describe a novel self-aligned technology, BSA (BSG Self-Aligned) technology. The BSA technology makes it possible to realize the self-aligned bipolar transistors having sub- 100nm deep base junction and to solve the problems in lateral and vertical scaling down of self-aligned transistors. The BSA technology is featured by the use of BSG film not only as a sidewall spacer but also as a diffusion source to form both the intrinsic base and p+-link regions by rapid thermal annealing (RTA), simultaneously. The typical BSA transistor having sub-100nm deep base junction showed 70 of hFE, 7V of BVCEOand 3V of BVEBO, respectively.

Submicron epitaxial layer and RTA technology for extremely high speed bipolar transistors

This paper will describe an extremely high speed bipolar transistor with which we achieved an ECL gate delay of as fast as 52ps. To realize the high speed transistor, a submicron epitaxial layer, 1µm ruled polysilicon self-aligned technology and rapid thermal annealing (RTA) technology were utilized. Using the scaled down transistor, optimization of RTA conditions and epitaxial layer thickness was investigated. The highest ECL gate speed was obtained under optimized conditions of 0.7µm thick epitaxial layer and RTA at 1050°C-10sec. The current density of the minimum gate delay point was 0.67mA/µm2. The cut-off frequency of the transistor was 13GHz.

A Si/SiGe heterojunction bipolar transistor with undoped SiGe spacer for CRYO-BiCMOS circuits

A heterojunction bipolar transistor (HBT) for BiCMOS circuits is described which can operate at liquid nitrogen (LN2) temperature (CRYO-BiCMOS). An HBT which has an n/sup +/-polysilicon/n-type Si epitaxial layer emitter structure on an undoped SiGe/p/sup +/ SiGe base structure, with both SiGe layers having a Ge fraction of 30%, has been developed to maintain the current gain and to reduce the emitter-base turn-on voltage at LN2 temperature. This HBT achieves a high current gain of 124 and a low turn-on voltage of 0.96 V at LN2 temperature. Under the conditions of 3.3 V supply voltage and 83 K, a 0.6 mu m CRYO-BiCMOS two-input NAND gate shows a basic gate delay of 200 ps.<<ETX>>

A CRYO-BiCMOS technology with Si/SiGe heterojunction bipolar transistors

A high-performance liquid-nitrogen temperature BiCMOS (CRYO-BiCMOS) technology with Si/SiGe heterojunction bipolar transistors (HBTs) is presented. The newly developed HBT, which has an n/sup +/-polysilicon/n-type Si epitaxial layer emitter structure on a p-type SiGe base layer, shows a high current gain of 50 at liquid nitrogen temperature. Under the conditions of 3.3 V and 83 K, the driving capability of CRYO-BiCMOS gates is two times larger than that of the CRYO-CMOS gate. At 3.3 V and a load capacitance of 1 pF, the gate delay of CRYO-BiCMOS gate with pull-up HBT is 480 ps. The CRYO-BiCMOS with Si/SiGe HBTs presented is very promising for the future progress of BiCMOS LSIs.<<ETX>>

Stoichiometric ECR SiO/sub 2/ interlayer for polysilicon emitter bipolar transistors using MBE system

The effect of SiO/sub x/ interlayer stoichiometry on polysilicon emitter bipolar transistors was investigated. By utilizing a newly developed electron cyclotron resonance (ECR) oxidation technology, SiO/sub x/ layers (1<x<=2) with different stoichiometries were prepared by changing oxidation temperature in a molecular beam epitaxy growth system. A stoichiometric SiO/sub 2/ layer can be obtained by ECR oxidation at room temperature SiO/sub x/ layer stoichiometries were evaluated by X-ray photoelectron spectroscopy. Using the ECR oxidation technology, an experimental polysilicon emitter transistor was prepared. The transistor, having a stoichiometric interfacial SiO/sub 2/ layer, showed a current gain of 70, which was three times larger than that of a conventional polysilicon emitter transistor.<<ETX>>

Self-Aligned Technology for Sub-100nm Deep Base Junction Transistors

The problems in scalling down of modern advanced polysilicon self-aligned transistors are brief1y discussed. Then, a novel self-aligned technology is proposed to solve the problems. The newly developed BSA (BSG Self-Aligned ) technology is featured by the use of CVD-BSG Film as a sidewall spacer as well as a diffusion source to form both intrinsic base and p+-connecting regions, simultaneousely. The fabricated transistor having 40nm deep emitter-base junction and sub-100nm collector-base junction shows 70 of hFE and 7V of BVCEO, respectively.