Kiyotaka Imai

The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling

This paper presents a new reliability scaling scenario for CMOS devices with direct-tunneling ultra-thin gate oxide. Device degradation due to bias-temperature instability (BTI) was studied. First, the stress voltage dependence of BTI results indicate that the direct-tunneling electron and/or hole transport does not play a major role in the degradation mechanism. Secondly, it was found that the threshold voltage change caused by BTI for the PMOSFET limits the device lifetime, which is shorter than that defined by hot-carrier induced degradation for the NMOSFET. It originates from the difference of supply voltage dependence between BTI and hot-carrier degradation.

NBTI enhancement by nitrogen incorporation into ultrathin gate oxide for 0.10-/spl mu/m gate CMOS generation

We investigated the degradation of device reliability due to Negative Bias Temperature Instability (NBTI) of PMOSFET with ultrathin gate oxide. It was experimentally demonstrated that the chemical reactions at the gate oxide/substrate interface and/or diffusion of hydrogen related species are the major cause of the NBTI. We also found that nitridation of gate oxide enhances NBTI. In order to suppress the NBTI, the density of hydrogen terminated silicon bond at the interface needs to be minimized. Thus, the concentration of nitrogen in thin gate oxide has to be optimized in terms of the reliability reduction due to NBTI.

Modelling temperature effects of quarter micrometre MOSFETs in BSIM3v3 for circuit simulation

This paper presents the temperature modelling in BSIM3v3 (Berkeley Short-channel IGFET Model version 3), and comparison with measured data for both n- and p-channel devices with a channel length down to a quarter of a micrometre from room temperature up to C. I - V, and are modelled with the temperature dependences of mobility, threshold voltage, saturation velocity and series resistance.

A 5 ns 1 Mb ECL BiCMOS SRAM

A 1 M-word*1-b emitter-coupled-logic (ECL) SRAM in 0.8- mu m BiCMOS technology that achieves 5-ns access time using (1) wired-OR predecoders, (2) ECL CMOS level converters with partial address decoding, and (3) sensing with small differential voltage swing on long read bus lines is described. The memory cell array is divided into two 512 K-cell subarrays. Each subarray consists of 16 32-kb arrays, each of which is organized into 256 rows and 128 columns. An X-decoder is located between a pair of 32-kb arrays. Address input signals are received by an ECL address buffer. The first circuit for address decoding is a wired-OR predecoder, which does the predecoding and predecoded signal line driving. Predecoded address signals with about 1.2-V voltage swing drive 16.5-mm predecoded lines between two 512-kb subarrays and are received by partial-decoding level converters at corresponding 32-kb arrays.<<ETX>>

Power-aware 65 nm node CMOS technology using variable V/sub DD/ and back-bias control with reliability consideration for back-bias mode

We have developed a power-aware CMOS technology featuring variable V/sub DD/ and back-bias control. Three typical operation modes are defined: high-speed mode (V/sub DD/ = 1.2V, V/sub B/ = 0V), nominal mode (V/sub DD/ = 0.9V, V/sub B/ = -0.5V) and power-save mode (V/sub DD/ = 0.6V, V/sub B/ = -2.0V). Compared with nominal mode, one and a half order of magnitude reduction of standby leakage current is achieved with power-save mode, while 75% higher drivability is achieved with high-speed mode. Device reliability for back-bias condition was also investigated. With higher back-bias, NBT (Negative Bias Temperature) degradation for pFET is enhanced especially in the case of thinner gate oxide. From activation energy, we believe the dominant mechanism is SHH (Substrate Hot-Hole) injection. Reduced V/sub DD/ at standby mode drastically alleviates this degradation caused by NBT stress and SHH injection. With appropriate V/sub DD/ and V/sub B/ combination, power-aware 65nm CMOS with sufficient reliability can be achieved.

A 100 nm node CMOS technology for practical SOC application requirement

Reports a 1.0 V operation 100 nm technology node CMOS technology for generic SOC application. We have estimated that for practical SOC chip/package design, target spec of both I/sub OFF/ and I/sub G/ must be below 5 nA//spl mu/m in view of heat generation issue. The key point is how to obtain higher drive current under this I/sub OFF//I/sub G/ restriction. Taking this criteria into account, we optimized 1) the gate dielectric formation sequence consisting of RTH treatment and radical nitridation; 2) gate off-set spacer optimization for practical and robust 100 nm-node CMOS technology. Fabricated transistor, featuring 65 nm gate length and 1.6nm-EOT gate dielectric, show 640/260 /spl mu/A//spl mu/m of I/sub ON/ and 5n/5n A//spl mu/m of I/sub OFF/ with 1.0V operation.

A unified MOSFET channel charge model for device modeling in circuit simulation

In this paper, we present a simple and accurate MOSFET channel charge model for device modeling in circuit simulation. The model can guarantee good continuities and smooth transitions of charge, capacitance, current, and transconductance from subthreshold to strong inversion with a unified analytical expression, and agrees with the experimental data well at various process and bias conditions from subthreshold and strong inversion, including the moderate inversion region of growing importance for low-voltage/power circuits.

L-C-band low-voltage BiCMOS MMICs for dual-mode cellular-LAN applications

This paper Is concerned with the design considerations and performance results for low-voltage Si monolithic microwave integrated circuits (MMICs) developed for mobile and personal communications applications. A 0.4 /spl mu/m ECL-BiCMOS process technology was employed to develop bipolar-based RF amplifiers, MOS-based IF amplifiers, BiCMOS-based simplified Gilbert mixers, and monolithic down-converter as well as upconverter ICs incorporating these elements. These converters are designed to operate at a bias voltage of 2 V over 1.8-6.2 GHz exhibiting a conversion gain of 35-15 dB with a variable IF frequency of up to several 100 MHz. Chip size for both the downconverter and upconverter ICs is 1.0 mm/spl times/0.7 mm.

A 70 nm gate length CMOS technology with 1.0 V operation

A 70-nm gate length CMOS technology for 1.0 V operation has been developed. This technology realizes high performance CMOS roadmap trend and utilizes sub-1 keV ion implantation for source/drain extension formations, quick-cooling RTA process, and ultra-thin gate dielectrics of 1.3 nm. The thickness of the gate dielectrics has been optimized in terms of both the I/sub ON/-I/sub OFF/, tradeoff and gate delay metrics. Obtained I/sub D//sup SAT/ for nMOS and pMOS are 723 /spl mu/A//spl mu/m (I/sub OFF/=16 nA//spl mu/m) and 290 /spl mu/A//spl mu/m (I/sub OFF/=20 nA//spl mu/m), respectively.

Design Methodology of Body-Biasing Scheme for Low Power System LSI With Multi-

We proposed a multi-Vth transistor design for a body-biasing scheme to control threshold voltage Vth variation and power consumption for the 65-nm node and beyond. One of the biggest barriers in applying the body biasing to multi-Vth transistors that have a different body-biasing sensitivity was solved by using a Hf-based gate dielectric work-function modulation combined with a careful channel design. The body-biasing sensitivities for multi-Vth transistors were successfully equalized, and the sensitivity is independent of the original Vth. By using the body biasing with the optimal transistor design, die-to-die Vth variation has been efficiently suppressed even for dies with multi-Vth transistors. As a result, both 50% total Vth variation reduction and 1/50 static random access memory standby current have been achieved. This design scheme can guarantee excellent performance for future low power applications because of its simplicity and its bulk-design compatibility.