M.D. Allen

PHENIX inner detectors

Abstract The timing, location and particle multiplicity of a PHENIX collision are determined by the Beam–Beam Counters (BBC), the Multiplicity/Vertex Detector (MVD) and the Zero-Degree Calorimeters (ZDC). The BBCs provide both the time of interaction and position of a collision from the flight time of prompt particles. The MVD provides a measure of event particle multiplicity, collision vertex position and fluctuations in charged particle distributions. The ZDCs provide information on the most grazing collisions. A Normalization Trigger Counter (NTC) is used to obtain absolute cross-section measurements for p–p collisions. The BBC, MVD and NTC are described below.

A multi-channel ADC for use in the PHENIX detector

A custom CMOS analog to digital converter was designed and a prototype 8-channel ADC ASIC was fabricated in a 1.2 /spl mu/m process. The circuit uses a Wilkinson-type architecture which is suitable for use in multi-channel applications such as the PHENIX detector. The ADC design features include a differential positive-ECL input for the high speed clock and selectable control for 11 or 12-bit conversions making it suitable for use in multiple PHENIX subsystems. Circuit topologies and ASIC layout specifics, including power consumption, maximum clock speed, INL, and DNL are discussed. The ADC performed to 11-bit accuracy.

A low-power, CMOS peak detect and hold circuit for nuclear pulse spectroscopy

A low-power CMOS peak detecting track and hold circuit optimized for nuclear pulse spectroscopy is presented. The circuit topology eliminates the need for a rectifying diode, reducing the effect of charge injection into the hold capacitor, incorporates a linear gate at the input to prevent pulse pileup, and uses dynamic bias control that minimizes both pedestal and droop. Both positive-going and negative-going pulses are accommodated using a complementary set of track and hold circuits. Full characterization of the design fabricated in 1.2 /spl mu/m CMOS including dynamic range, integral nonlinearity, droop rate, pedestal, and power measurements is presented. The circuit operates with only 250 /spl mu/w for input pulses with 7 /spl mu/s peaking time. Power consumption was increased to 750 /spl mu/w for driving off-chip and test system capacitances. Analysis and design approaches for optimization of operational characteristics are also discussed. >

Charge sensitive preamplifier and pulse shaper using CMOS process for germanium spectroscopy

The authors have developed a low noise, low power charge sensitive amplifier and pulse shaping circuit. The application is for a double-sided germanium strip detector, nominally providing 50 independent spectroscopy channels. An array of these detectors would provide significant improvements in imaging, spectroscopy and sensitivity for space-based gamma-ray astronomy. The key features of these electronics are low noise, very low power, and a small footprint per channel. Performance of the first circuit is in good agreement with simulations, with /spl sim/205e noise rms (0 pF), and 3 mW/channel power consumption. The dynamic range is 0-3.3 MeV (germanium) with a linearity of /spl plusmn/0.6%. Performance of this prototype device is discussed. >

Design and performance of beam test electronics for the PHENIX Multiplicity Vertex Detector

The system architecture and test results of the custom circuits and beam test system for the Multiplicity-Vertex Detector (MVD) for the PHENIX detector collaboration at the Relativistic Heavy Ion Collider (RHIC) are presented in this paper. The final detector per-channel signal processing chain will consist of a preamplifier-gain stage, a current-mode summed multiplicity discriminator, a 64-deep analog memory (simultaneous read-write), a post-memory analog correlator, and a 10-bit 5 /spl mu/s ADC. The Heap Manager provides all timing control, data buffering, and data formatting for a single 256-channel multi-chip module (MCM). Each chip set is partitioned into 32-channel sets. Beam test (16-cell deep memory) performance for the various blocks will be presented as well as the ionizing radiation damage performance of the 1.2 /spl mu/ n-well CMOS process used for preamplifier fabrication.

A flexible analog memory address list manager for PHENIX

A programmable analog memory address list manager has been developed for use with all analog memory-based detector subsystems of PHENIX. The unit provides simultaneous read/write control, cell write-over protection for both a Level-1 trigger decision delay and digitization latency, and re-ordering of AMU addresses following conversion, at a beam crossing rate of 105 ns. Addresses are handled such that up to 5 Level-1 (LVL-1) events can be maintained in the AMU without write-over. Data tagging is implemented for handling overlapping and shared beam-event data packets. Full usage in all PHENIX analog memory-based detector subsystems is accomplished by the use of detector-specific programmable parameters-the number of data samples per valid LVL-1 trigger and the sample spacing. Architectural candidates for the system are discussed with emphasis on implementation implications. Details of the design are presented including application specifics, timing information, and test results from a full implementation using field programmable gate arrays (FPGAs).

Development of a front end controller/heap manager for PHENIX

PHENIX FEMs have three classifications: Type I A controllerheap manager has been designed for applicability to all detector subsystem types of PHENIX. The heap manager performs all functions associated with front end electronics control including ADC and analog memory control, data collection, command interpretation and execution, and data packet forming and communication. Interfaces to the unit consist of a timing and control bus, a serial bus, a parallel data bus, and a trigger interface. The topology developed is modular so that many functional blocks are identical for a number of subsystem types. Programmability is maximized through the use of flexible modular functions and implementation using field programmable gate arrays (FPGAs). Details of unit design and functionality will be discussed with particular detail given to subsystems having analog memory-based front end electronics. In addition, mode control, serial functions, and FPGA implementation details will be presented.

Timing and control requirements for a 32-channel AMU-ADC ASIC for the PHENIX detector

A custom CMOS Application Specific Integrated Circuit (ASIC) has been developed consisting of an analog memory unit (AMU) and analog to digital converter (ADC), both of which have been designed for applications in the PHENIX experiment. This IC consists of 32 pipes of analog memory with 64 cells per pipe. Each pipe also has its own ADC channel. Timing and control signal requirements for optimum performance are discussed in this paper.

Low noise, low power dissipation analog LSI electronics for heavy ion detectors

The work performed to date for the Multiplicity-Vertex Detector (MVD) for the PHENIX detector collaboration at the Relativistic Heavy Ion Collider (RHIC) is presented in this paper. Composed of approximately 34,000 channels of both silicon strips and silicon pads, the detector per-channel signal processing chain consists of a preamplifier-gain stage, a current-mode summed multiplicity discriminator, a 64-deep analog memory (simultaneous read-write), an analog correlator and a 10-bit 5 /spl mu/s ADC. All timing control, data buffering, and data formatting for a single 256-channel multi-chip module (MCM) is performed by the system controller or Heap Manager. Each chip set is partitioned into 32-channel sets. Prototype performance for the various blocks will be presented as well as the ionizing radiation damage performance of the 1.2 /spl mu/ nwell CMOS process used for fabrication.

CMOS readout system for a double-sided germanium strip detector

A wide variety of applications require a hard X-ray or gamma ray detector which combine both good spatial resolution and energy resolution. Double-sided solid-state strip detectors provide this capability, We report on the development of CMOS electronics designed for photon detection with strip detectors. These electronics include a low noise preamplifier, semi-gaussian shaping amplifier, discriminator, and peak detection circuitry. All circuits are designed to operate at low power. Circuits have been duplicated in both NMOS and PMOS to provide both polarities of signals. We have constructed an 8/spl times/8 channel system to test these prototype chips. Power consumption for the preamplifier through peak-detector circuit is 4 mW/channel. The test system has a conversion gain of /spl sim/35 mV/fC, system noise (equivalent noise charge) of ENC<220 e rms (0 pF), and a dynamic range of >100:1 in both NMOS and PMOS circuits.