Madhav P. Desai

On the connectivity in finite ad hoc networks

Connectivity and capacity analysis of ad hoc networks has usually focused on asymptotic results in the number of nodes in the network. In this letter we analyze finite ad hoc networks. With the standard assumption of uniform distribution of nodes in [0, z], z > 0, for a one-dimensional network, we obtain the exact formula for the probability that the network is connected. We then extend this result to find bounds for the connectivity in a two-dimensional network in [0, z]/sup 2/.

Sizing of clock distribution networks for high performance CPU chips

In a high performance microprocessor such as Digitals 30O MHz Alpha 21164, the distribution of a high quality clock signal to all regions of the device is achieved using a complex grid with multiple drivers. The large capacitance of this distribution grid together with the high clock frequency results in substantial power dissipation in the chip. In this paper, we describe techniques to size the interconnect segments (thus reducing their capacitance) of the distribution network while meeting certain design goals. These techniques place no restrictions on the topology of the network being sized, and have been successfully used on very large examples.

A characterization of the smallest eigenvalue of a graph

It is well known that the smallest eigenvalue of the adjacency matrix of a connected d-regular graph is at least − d and is strictly greater than − d if the graph is not bipartite. More generally, for any connected graph G = (V, E), consider the matrix Q = D + A where D is the diagonal matrix of degrees in the graph G and A is the adjacency matrix of G. Then Q is positive semidefinite, and the smallest eigenvalue of Q is 0 if and only if G is bipartite. We will study the separation of this eigenvalue from 0 in terms of the following measure of nonbipartiteness of G. For any S ⊆ V, we denote by emin(S) the minimum number of edges that need to be removed from the induced subgraph on S to make it bipartite. Also, we denote by cut(S) the set of edges with one end in S and the other in V − S. We define the parameter Ψ as ***image*** The parameter Ψ is a measure of the nonbipartiteness of the graph G. We will show that the smallest eigenvalue of Q is bounded above and below by functions of Ψ. For d-regular graphs, this characterizes the separation of the smallest eigenvalue of the adjacency matrix from −d. These results can be easily extended to weighted graphs.

The effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performance

The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (K/sub gate/) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is observed that there is a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance in addition to an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by a high-K gate dielectric. The lower parasitic outer fringe capacitance is beneficial for the circuit performance, while the increase in internal fringe capacitance and the decrease in the gate-to-channel capacitance will degrade the short channel performance contributing to higher DIBL, drain leakage, and lower noise margin. It is shown that using low-K gate sidewalls with high-K gate insulators can decrease the fringing-induced barrier lowering. Also, from the circuit point of view, for the 70-nm technology generation, the presence of an optimum K/sub gate/ for different target subthreshold leakage currents has been identified.

Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors

In deep submicrometer MOSFETs the device performance is limited by the parasitic capacitance and resistance. Hence a circuit model is needed to treat these effects correctly. In this work, we have developed circuit models for the parasitic capacitances in conventional and high-K gate dielectric MOS transistors by taking into account the presence of source/drain contact plugs. The accuracy of the model is tested by comparing the modeled results with the results obtained from three-dimensional (3-D) Monte-Carlo simulations and two-dimensional (2-D) device simulations over a wide range of channel length and oxide thickness. The model is also used to study the dependence of parasitic capacitance on gate length, gate electrode thickness, gate oxide thickness, gate dielectric constant, and spacer width.

The effect of LAC doping on deep submicrometer transistor capacitances and its influence on device RF performance

In this paper, we have systematically investigated the effect of lateral asymmetric doping on the MOS transistor capacitances and compared their values with conventional (CON) MOSFETs. Our results show that, in lateral asymmetric channel (LAC) MOSFETs, there is nearly a 10% total gate capacitance reduction in the saturation region at the 100-nm technology node. We also show that this reduction in the gate capacitance contributes toward improvement in f/sub T/, f/sub max/, and RF current gain, along with an improved transconductance in these devices. Our results also show that reduced short-channel effects in LAC devices improve the RF power gain. Finally, we report that the lateral asymmetric channel doping gives rise to a lower drain voltage noise spectral density compared to CON devices, due to the more uniform electric field and electron velocity distributions in the channel.

Variance reduction in Monte Carlo capacitance extraction

In this article we address efficiency issues in implementation of Monte Carlo algorithm For 3D capacitance extraction. Error bounds in statistical capacitance estimation are discussed. Methods to tighten them through variance reduction techniques are detailed. Sample values in implementation of Monte Carlo algorithm are completely determined by the first hop in random walk. This in turn facilitates application of variance reduction techniques like importance sampling and stratified sampling to be used effectively. Experimental results indicate average speedup of 16X in simple uniform dielectric technologies, 7.3X in technologies with layers of dielectrics and 4.6X in technologies having conformal dielectrics.

On the convergence of block relaxation methods for circuit simulation

The authors developed sufficient conditions for the convergence of several block relaxation methods. They first consider time-point relaxation methods, namely the block Gauss-Seidel-Newton (G-S-N) and the block Newton-Gauss-Seidel (N-G-S) algorithms. The previously known sufficient condition for convergence of the G-S-N and the N-G-S algorithms requires: (1) a capacitor connected between every node in the circuit and the reference ground node: and (2) the choice of a sufficiently small time step for the implicit integration formula used to discretize (in time) the circuit equations. The authors derive a sufficient condition that is less restrictive than (1) above. For a given partitioning of a circuit, they define a set (possibly empty) of feedback nodes that capture the topology of the partitioned circuit to a certain extent. They then show that the G-S-N and the N-G-S algorithms converge. >

Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches

In this paper, we use circuit simulations to characterize the effects of technology scaling on the metastability parameters of CMOS latches used as synchronizers. We perform this characterization by obtaining a synchronization error probability curve from a histogram of the latch delay. The main metastability parameters of CMOS latches are /spl tau//sub m/ and T/sub w/. /spl tau//sub m/ is the exponential time constant of the rate of decay of metastability and T/sub w/ is effective metastability window size at a normal propagation delay. Both parameters can be extracted from a histogram of the latch delay. This paper also explains a way to calibrate the simulator for accuracy. The simulations indicate that /spl tau//sub m/ scales better than the technology scale factor. T/sub w/ also scales down but its factor cannot be estimated as well as that of /spl tau//sub m/. This is because T/sub w/ is a complex function of signal and clock edge rate and logic threshold level.

A systematic technique for verifying critical path delays in a 300 MHz Alpha CPU design using circuit simulation

A static timing verifier is an important tool in the design of a complex high performance VLSI chip such as an Alpha CPU. A timing verifier uses a simple and pessimistic delay model to identify critical failing paths in the design, which then need to be fixed. However, the pessimistic delay model results in a large number of correct paths being identified as failing paths, possibly leading to wasted design resources. Therefore, each critical path identified by the timing verifier needs to be analyzed using a circuit simulator such as SPICE in order to confirm that it is a real failure. Setting up such a simulation is complex, especially when the critical path consists of structures appearing in a datapath of the CPU. In this paper, we present algorithms for the construction of a model for simulating the maximum delay through a critical path. This technique has been used to analyze several critical paths during the design of a 300 MHz Alpha CPU.