Bulusu Anand

Vertical Silicon Nanowire Gate-All-Around Field Effect Transistor Based Nanoscale CMOS

In this letter, we investigate a novel vertical silicon nanowire-based (NW) complementary metal-oxide-semiconductor (CMOS) technology for logic applications. The performance and the behavior of two- and single-wire CMOS inverters are simulated and analyzed. We show that vertical NW based CMOS offers a reduction of up to 50% in layout area, along with delay reductions of 50% (two wire) and 30% (single wire) compared with fin-shaped field effect transistor (FinFET) technology. The results show that vertical NW CMOS technology has a very high potential for ultralow-power applications with a power saving of up to 75% and offers an excellent overall performance for deca-nanoscale CMOS.

Vertical Nanowire CMOS Parasitic Modeling and its Performance Analysis

In this paper, the analytical models of parasitic resistance and capacitance of vertical nanowire (VNW) FET are presented, considering device structural asymmetry. These models are then used to analyze the effect of channel, source-drain extension lengths, and nanowire diameter on device and VNW CMOS performance for 15 nm node. We find that the asymmetry in structure (between top and bottom electrodes) leads to asymmetric parasitic resistances and capacitances that play an important role in determining the circuit delays. Thus our models help to quantify the role of parasitics on VNW device and CMOS performance having device asymmetry. Further, these parasitic models have high potential for use in developing a compact model of a complete device for VNW circuit simulations.

Silicon film thickness considerations in SOI-DTMOS

We study the body effect in silicon-on-insulator (SDI) devices to determine if enhanced drive currents can be obtained with a body bias equal to the supply voltage. We find that significantly enhanced drive currents are observed only when the film thickness is sufficiently large. We explain this phenomenon using two-dimensional (2-D) device simulations and conclude that a film thickness greater than 100 nm is required. This sets a criterion for SOI devices to be used as dynamic threshold MOSFETs.

Device Circuit Co-Design Issues in Vertical Nanowire CMOS Platform

In this letter, we investigate the effect of device and layout parasitics on circuit performance of vertical nanowire (VNW) CMOS technology. We evaluate the effect of source-drain extension (S/Dext) scaling and device asymmetry on device and circuit performances for 15 nm VNW CMOS. It is seen that, due to reduced series resistance, circuit delay continues to improve with S/Dext down to 10 nm, despite increased parasitic capacitances. Also, we show that asymmetry between top and bottom electrodes plays a strong role in determining circuit delay, while layout-dependent parasitics are of secondary importance. The results show that delay is increased by 65% with top electrode as source, which is attributed to increase in series resistance and gate-drain overlap capacitances. The comparison of VNW and FinFET CMOS shows nearly 40% delay reduction, highlighting excellent potential of VNW CMOS for 15 nm and below technology nodes.

Effect of Load Capacitance and Input Transition Time on FinFET Inverter Capacitances

FinFETs are poised to replace conventional MOSFETs at sub-22-nm technology nodes mainly due to their relatively planar compatible fabrication process. It is well known that FinFET device parasitics are critical for the propagation delay and power dissipation. However, a quantitative understanding of device parasitics for circuit design is yet to be attained. We report a new extension transistor-induced capacitance shielding (ETICS) phenomenon. In this phenomenon, the FinFET extension region forms a transistor, which shields gate-extension fringing field capacitance. Due to this phenomenon, we observe a strong dependence of effective values of FinFET logic gate capacitances on transition times of their terminal voltages, which is unlike the conventional transistors. We show that delay estimation methods need to be modified considering ETICS for efficient FinFET circuit design.

Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performance

This paper investigates the circuit performance improvement through poly-pitch scaling in strain engineered devices. We use tensile contact etch stop liner(t-CESL), compressive contact etch stop liner(c-CESL), embedded SiC and SiGe as stress sources in NMOS and PMOS devices. It is observed that poly-pitch optimization delivers ~18% and ~13% reduction in delay of an inverter driving FO4 and FOl loads respectively. We observe that, in the presence of process induced mechanical stress; the optimum poly-pitch depends upon the size of the driver and the load. Finally, we present a model for choosing optimum poly-pitch for enhanced circuit performance while taking care of the power constraint.

Gate-Pitch Optimization for Circuit Design Using Strain-Engineered Multifinger Gate Structures

Optimal transistor sizing and layout using multifinger gate structures (MFGSs) in mechanical stress-engineered CMOS technology is a major issue. We observe that the pull-down and pull-up delay of an inverter using seven-fingered devices with fan-out-of-four (FO4) load increases by ~ 9% and ~ 14%, respectively, compared with the FO4 delay of a reference inverter using single-finger gate structure. On the other hand, doubling gate-pitch in the above inverter improves the pull-down and pull-up delay by ~ 18% and ~ 23%, respectively, compared with the delay of the reference inverter. In this brief, we present a methodology of transistor sizing and layout optimization for MFGSs in stress-engineered CMOS circuits. For this, we derive and validate a modified model of logical effort (LE), where LE is expressed as a function of the number of fingers (NF) and gate-pitch (Lpp). Using our model, we reduce the error in the estimated delay of a four-stage buffer with FO4 from ~ 9% to ~ 1%. Using our methodology, we improve the circuit performance by 7%.

Efficient nanoscale VLSI standard cell library characterization using a novel delay model

Accurate estimation of delays in Static Timing Analysis (STA) using Non Linear Delay Model (NLDM) based Look Up Table (LUT) is a major challenge in nanometer range VLSI circuits. Issues with NLDM based LUT are mostly due to the arbitrary choice of input signal transition time trin and load capacitance (Cl) and the large number of simulations to be performed for characterizing an entire standard cell library. In this paper, we present a systematic method to reduce standard cell library characterization time significantly. For this purpose we propose and use a simple and physically reasonable logic gate delay model in which delay varies linearly with Cl and trin. We also determine its region of validity in the (Cl, trin) space. We express the delay model coefficients and its region of validity as a function of inverter (or logic gate) size. We do not use device current/capacitance models in our work and hence the method is general enough to be used with scaling. With the help of this new model proposed, We were able to save approximately of 51% SPICE simulations during the standard cell library characterization. We observe that the delay obtained using our LUTs is as accurate as that of the delay obtained through traditional LUTs.

Spacer Engineering-Based High-Performance Reconfigurable FET With Low OFF Current Characteristics

In this letter, we optimize and investigate for the first time the effect of source/drain spacer oxide on the performance of a dual gate ambipolar silicon nanowire field effect transistor. Using extensive 3-D TCAD simulations, we show that the OFF-state leakage can be reduced by more than two orders of magnitude owing to the combined use of HfO2 spacer and high-κ gate dielectric, resulting in an enhanced ON/OFF current ratio >1011 for both n and p-FET as compared with reported values of ~109. Comparing with the existing experimental dual and trigate ambipolar devices, 64.1% improvement in subthreshold slope for n-FET and 61.8% (40.9%) for n (p-FET) are observed. Having, an improvement in the ON-state current with JDmax of 767.51 (263.05) kA/cm-2 for n-FET (pFET), the device promises excellent ultra low power logic performance, with ambipolarity.

Novel Design Methodology Using

In this paper, the impact of nanowire source/drain extension, diameter, and channel length on nanowire (NW) device performance is investigated. We present a novel approach using the extension length as tuning parameter to match the drive current of n- and p-FET in NW CMOS logic applicable down to 10-nm gate length. Our approach overcomes the drive matching issue in NW/FinFET based CMOS circuits. We show that, in comparison to conventional CMOS, where the number of NWs/fins in p-FET is used to match n-FET drive, the proposed approach provides a significant reduction in circuit active area and power dissipation. When compared to conventional CMOS inverter, the proposed approach shows 20% lower area, and 35% saving in power in case of NW CMOS inverter. Our results show that extension length tuned-CMOS has an excellent option for low-power applications in both NW and FinFET technologies.