Mahbub Rashed

Challenges of analog and I/O scaling in 10nm SoC technology and beyond

Continuous process-level and system-level innovation has driven Moores Law scaling for the last fifty years, and will continue to do so in the next decades. In the last two decades, there has been an acceleration of new materials and devices into semiconductor manufacturing, such as low-k, strained Si, high-k, and FinFET, in order to continue process and cost scaling. At the same time, ever increasing component integration on SoCs has further driven cost scaling, allowing the current mobile era to take shape. In the next decade, the focus of SoC innovation will be on patterning and low-resistance materials on the process side, and multi-die package integration on the system side.

Design space analysis of novel interconnect constructs for 22nm FDX technology

In this paper, we describe an integrated design space analysis approach consisting of full factorial layout generation, lithography simulations with added proximity effects, and rigorous statistical analysis through monte-carlo simulations which is used in the evaluating interconnects. This agile Design rule development process provides a quick turnaround time to down-select the potential layout configurations that can offer a competitive, robust and reliable design and manufacturing. Further layout and placement optimization is carried out to evaluate intra-cell, inter-cell and cell boundary situations, which are critical for a place and routed block. These interconnects developed using the integrated approach has been the key contributor to give 20-30% higher performance at the same Iddq leakage for 8T libraries compared to Single Diffusion break or Double Diffusion break based 12T libraries in 22FDX Technology.