Yunfei Deng

Decomposition strategies for self-aligned double patterning

Spacer technology, a self-aligned double patterning (SADP) technique, has been drawing more and more attention due to its less stringent overlay requirements compared to other double-patterning methods. However, use of SADP techniques was previously limited by the lack of flexibility in terms of decomposition options , and significant developments were mainly implemented for 1D-type applications for memory. In this paper, we extend the SADP technique into the logic field. A matrix of design rule extraction structures was created by GLOBALFOUNDRIES, which was then decomposed into 2-mask SADP patterning solutions by Cadence Design Systems, and wafers were manufactured by Applied Materials. The wafers were processed in both positive and negative spacer tones, and then we evaluate the design capabilities of SADP for logic BEOL patterning on pitches from 56nm to 64nm. It shows that the SADP has big advantage over other pitch splitting techniques such as LELE in terms of design rules, overlay, and CD uniformity control. With SADP, the most challenging design rules for BEOL such as tip-to-tip and tip-to-line can be reduced 50% from 80 nm to 40 nm.

Resist pattern prediction at EUV

Accurate and flexible simulation methods may be used to further a researchers understanding of how complex resist effects influence the patterning of critical structures. In this work, we attempt to gain insight into the behavior of a state-of-the-art EUV resist through the use of stochastic resist simulation. The statistics of photon and molecule counting are discussed. A discrete, probabilistic ionization and electron scattering simulator for acid generation at EUV is discussed. At EUV, acid generators are hypothesized to be activated by secondary electrons yielded by ionization of the resist upon absorption of photons. Model fit to experimental data of mean CD and LWR for a state-of-the-art EUV resist is shown.

EUV lithography at the 22nm technology node

We are evaluating the readiness of extreme ultraviolet (EUV) lithography for insertion into production at the 15 nm technology node by integrating it into standard semiconductor process flows because we believe that device integration exercises provide the truest test of technology readiness and, at the same time, highlight the remaining critical issues. In this paper, we describe the use of EUV lithography with the 0.25 NA Alpha Demo Tool (ADT) to pattern the contact and first interconnect levels of a large (~24 mm x 32 mm) 22 nm node test chip using EUV masks with state-of-the-art defectivity (~0.3 defects/cm2). We have found that: 1) the quality of EUVL printing at the 22 nm node is considerably higher than the printing produced with 193 nm immersion lithography; 2) printing at the 22 nm node with EUV lithography results in higher yield than double exposure double-etch 193i lithography; and 3) EUV lithography with the 0.25 NA ADT is capable of supporting some early device development work at the 15 nm technology node.

Considerations in Source-Mask Optimization for Logic Applications

In the low k1 regime, optical lithography can be extended further to its limits by advanced computational lithography technologies such as Source-Mask Optimization (SMO) without applying costly double patterning techniques. By cooptimizing the source and mask together and utilizing new capabilities of the advanced source and mask manufacturing, SMO promises to deliver the desired scaling with reasonable lithography performance. This paper analyzes the important considerations when applying the SMO approach to global source optimization in random logic applications. SMO needs to use realistic and practical cost functions and model the lithography process with accurate process data. Through the concept of source point impact factor (SPIF), this study shows how optimization outputs depend on SMO inputs, such as limiting patterns in the optimization. This paper also discusses the modeling requirements of lithography processes in SMO, and it shows how resist blur affect optimization solutions. Using a logic test case as example, the optimized pixelated source is compared with the non-optimized source and other optimized parametric sources in the verification. These results demonstrate the importance of these considerations during optimization in achieving the best possible SMO results which can be applied successfully to the targeted lithography process.

Double patterning compliant logic design

Double patterning technology (DPT) is the only solution to enable the scaling for advanced technology nodes before EUV or any other advanced patterning techniques become available. In general, there are two major double patterning techniques: one is Litho-Etch-Litho-Etch (LELE), and the other is sidewall spacer technology, a Self-Aligned Double Patterning technique (SADP). While numerous papers have previously demonstrated these techniques on wafer process capabilities and processing costs, more study needs to be done in the context of standard cell design flow to enable their applications in mass production. In this paper, we will present the impact of DPT on logic designs, and give a thorough discussion on how to make DPT-compliant constructs, placement and routing using examples with Cadences Encounter Digital Implementation System (EDI System).

Efficient multi-die placement for blank defect mitigation in EUV lithography

Due to the absence of defect-free blanks in extreme ultraviolet (EUV) lithography, defect mitigation is necessary before mass production. One effective way to mitigate the defect impact is to increase the distance between the defects and feature boundaries such that the defects will not affect the printing of the features. Some algorithms have been developed to move the whole layout within the exposure field in order to avoid all defect impact. However, in reality the die size is usually much smaller than the exposure field, such that one blank is packed with multiple copies of the die, and each die can be placed independently within the exposure field. In this paper, we develop an EUV reticle placement algorithm to maximize the number of valid dies that are immune to defects. Given the layout of a die and a defective blank, we first apply a layout relocation algorithm to find all feasible regions for the die on the blank. Then we develop an efficient placement algorithm to place the dies within the feasible regions one at a time until all feasible regions are fully occupied. The simulation results show that our algorithm is able to find a solution efficiently and the number of valid dies placed by our algorithm is very close to the optimal solution.

DPT restricted design rules for advanced logic applications

Double patterning technology (DPT) provides the extension to immersion lithography before EUV lithography or other alternative lithography technologies are ready for manufacturing. Besides the additional cost due to DPT processes over traditional single patterning process, DPT design restrictions are of concerns for potential additional design costs. This paper analyzes design restrictions introduced by DPT in the form of DPT restricted design rules, which are the interface between design and technology. Both double patterning approaches, Litho-Etch-Litho-Etch (LELE) and Self-Aligned Double Patterning with spacer lithography (SADP), are studied. DPT design rules are summarized based on drawn design layers instead of decomposed layers. It is shown that designs can be made DPT compliant designs if DPT design rules are enforced and DPT coloring check finds no odd cycles. This paper also analyzes DPT design rules in the design rule optimization flow with examples. It is essential to consider DPT design rules in the integrated optimization flow. Only joint optimization in design rules between design, decomposition and process constraints can achieve the best scaled designs for manufacturing. This paper also discusses DPT enablement in the design flow where DPT aware design tools are needed so that final designs can meet all DPT restricted design rules.

Modeling and Characterization of Contact-Edge Roughness for Minimizing Design and Manufacturing Variations in 32-nm Node Standard Cell

Despite intensive attention on line-edge roughness (LER), contact-edge roughness (CER) has been relatively less studied. Contact patterning is one of the critical steps in a state-of-the-art lithography process; meanwhile, the design rule shrinking leads to larger CER in contact holes. Since source/drain (S/D) contact resistance depend on contact area and shape, larger CER results in significant change in a device current. In this paper, we first propose a CER model based on power spectral density function which is a function of RMS edge roughness, correlation length, and fractal dimension. Then, we present a comprehensive contact extraction methodology for analyzing process-induced CER effects on circuit performance. In our new contact extraction model, we first dissect the contact with a same distance, and then calculate the effective resistance considering both the shape weighting factor and the distance weighting factor for stress induced CMOS cells. Using the results of CER, we analyze the impact of CER variation on the S/D contact resistance and the device saturation current. Results show that when the rms value of CER is 10nm, the S/D contact resistance and the device saturation current can vary by as much as 57.8% and 2.1%, respectively.

Lithography target optimization with source-mask optimization

In the very low k1 regime in optical lithography, aggressive RET such as strong off-axis illumination causes significant forbidden pitches and lithography hotspots for aggressive designs. Various lithography retargeting techniques have been introduced to mitigate these process window failures. This paper proposes to bring the lithography target optimization into the Source-Mask Optimization (SMO) flow to achieve better SMO solutions at an earlier process development stage. Through this tight integration of lithography target optimization and source mask optimization, lithography target, source, and mask can be tuned together to provide the best overall process window for the newly defined targets. This improvement is demonstrated using a simple SMO test case for the 20-nm metal layer. Then at the later development stage, retargeting rules can be extracted from these optimized lithography targets, and they can be applied in the normal mask optimization process. This lithography target optimization flow can provide a faster tuning process for the lithography target rules at an early process development stage, and can provide optimized retarget rules for mask optimization process too. New challenges for retargeting in double patterning lithography are also discussed.

Optimization on illumination source with design of experiments

In advanced photolithography process for manufacturing integrated circuits, the critical pattern sizes that need to be printed on wafer are much smaller than the wavelength. Thus, source optimization (SO) techniques play a critical role in enabling a successful technology node. However, finding an appropriate illumination configuration involves intensive computation simulations. EDA vendors have been developing the pixelated source optimization tools that co-optimize both source and mask for a set of patterns. As an alternative approach, we have introduced design of experiments (DOE) methodology for parameterized source optimization to minimize computation efforts while achieving comparable CDU control for given design patterns. In this paper, we present a Response Surface Methodology (RSM) that simplifies the response function and achieves the optimization goal on multiple responses. Results have shown that the optimal input settings identified by this approach are comparable with the pixelated source optimization results.