Maher Soueidan

Direct Copper Bonding for Power Interconnects: Design, Manufacturing, and Test

3-D power module structures allow for better cooling and lower parasitic inductances compared with the classical planar technology. In this paper, we present a 3-D technology that uses an innovative assembly method (direct copper-to-copper bonding). The concept and manufacturing process of this technology is described in detail. An accurate electrical characterization is then performed to compare its performance with that of the classical planar structures.

Very Low Interface State Density From Thermally Oxidized Single-Domain 3C–SiC/6H–SiC Grown by Vapour–Liquid–Solid Mechanism

The temperature- and frequency-dependent electrical properties of SiO2/3C–SiC/6H–SiC structures have been studied. Capacitance measurements indicate that the single-domain 3C–SiC film is doped with an average concentration of 8.4×1016 cm-3. One nitrogen donor level and a shallow donor level were found. The measured interface state density near the conduction band edge of 3C–SiC is below 1011 cm-2 eV-1 and increases towards mid-gap as obtained from conductance and capacitance measurements. Our results are consistent with the assumption that the interfaces of SiO2/n-type SiC consist of two different kinds of interface traps.

A Lab-Scale Alternative Interconnection Solution of Semiconductor Dice Compatible with Power Modules 3-D Integration

Increase in the power density of power modules requires an interconnection technology alternative to wire-bonding technology. Emerging interconnection technologies allow a 3-D packaging of power modules. A proposal of interconnection solution for the power semiconductor dice is presented here; it is based on copper microposts that are electroplated on topside of the die. The die with its microposts is then attached to a top direct-bonding copper (DBC) substrate using a copper/tin transient liquid phase technique. The assembly of the backside of the die to a bottom DBC substrate is processed concurrently using the same transient liquid phase technique. The benefits or limitations of the substrate on the assembly are not discussed in this letter. Manufacturing and electrical characterization of a power semiconductor die with the microposts interconnection is presented in detail.

Application of the Spark Plasma Sintering Technique to Low-Temperature Copper Bonding

Planar structures, in which a power die is soldered on a substrate and wirebonds are used to connect the top of the die with the substrate, are limited in terms of thermal management and power density. 3-D packaging techniques have been proposed to overcome these limits. Here, an innovative copper-to-copper bonding solution is presented, that can be used for 3-D packaging. The bonding process is described and the effect of the bonding parameters is investigated. It is found that this technique is compatible with the requirements of power electronic packaging. A test assembly including a silicon power die and ceramic substrates is presented.

Modeling, Fabrication, and Characterization of Planar Inductors on YIG Substrates

This paper presents the design, fabrication, and characterization of micro planar inductors on a microwave magnetic material (YIG). Planar spiral inductors were designed for monolithic DC-DC converters in System-In-Package with 100 MHz switching frequency (1 W, Vin= 3.6 V, Vout= 1 V). A microwave magnetic substrate (YIG) serves as mechanical support, and also presents a double purpose by increasing inductance value and reducing electromagnetic interferences (EMI). This last point is critical to improve the behavior of a switching mode power supply (SMPS). In order to obtain an optimal design for the inductor, geometrical parameters were studied using Flux2D simulator and an optimized 30 to 40 nH spiral inductor with expected 25 mΩ RDC, 3 mm2 footprint area was designed. Subsequently, samples have been fabricated by electroplating technique, and tested using a vector network analyzer in the 10 MHz to 100 MHz frequency range. Results were then compared to the predicted response of simulated equivalent model.

A Study on the Temperature of Ohmic Contact to p-Type SiC Based on Ti 3 SiC 2 Phase

In this paper, the electrical properties of Ti₃SiC₂-based ohmic contacts formed on p-type 4H-SiC were studied. The growth of Ti₃SiC₂ thin films were studied onto 4H-SiC substrates by thermal annealing of Ti-Al layers deposited by magnetron sputtering. In this study, we varied the concentrations of Ti and Al (Ti₂₀Al₈₀, Ti₃₀Al₇₀, Ti₅₀Al₅₀, and Ti), and the annealing temperature from 900 °C to 1200 °C for each concentration. X-ray diffraction and transmission electron microscopy analyzes were performed on the samples to determine the microstructure of the annealed layers and to further investigate the compounds formed after annealing. Using the transfer length method structures, the specific contact resistance (SCR) at room temperature of all contacts was measured. The temperature dependence up to 600 °C of the SCR of the best contacts was studied to understand the current mechanisms at the Ti₃SiC₂/SiC interface. The experimental results are in agreement with the thermionic field emission theory. With this model, the barrier height of the contact varies between 0.71 and 0.85 eV. Finally, ageing tests showed that Ti₃SiC₂-based contacts were stable and reliable up to 400 h at 600 °C under Ar.

Elaboration of Architectured Materials by Spark Plasma Sintering

Spark plasma sintering has been used for decades in order to consolidate a wide variety of materials and permitting to obtain fully dense specimens. This technique has been mainly applied to ceramics. This paper concentrates on an unusual use of spark plasma sintering system: obtaining innovative materials especially architectured ones. Different applications are presented. Firstly, the SPS technique has been used to elaborate nanometers grain size materials or containing nanoscale microstructure. This is possible since the sintering temperature and the holding time are far lower in the SPS compared to other techniques. Then SPS has been used to realize diffusion bonding. In that case again, bonding can be realized at low temperature and for short time. It permits for example to realize bonding between two copper layers which is of a great importance for microelectronic applications. It is worth noting that this bonding can have the same mechanical strength as pure copper even for diffusion time of a few minutes. Secondly, bonding has been also carried out between a metallic layer and a ceramic one. This could lead to design of new layered materials combining interesting properties in terms of mechanical strength but also in terms of electrical resistance. The SPS machine has also been used to obtain porous materials (cobalt alloys or copper) with an adapted microstructure (porosity, tortuosity,). These structures could open new perspectives for biomedical or for microelectronic applications. All these examples lead to a better understanding of the physical processes which happen during spark plasma sintering.

Optical Study of Ge Incorporation in Cubic SiC Layers Grown by VLS

We report an optical study of 3C-SiC layers grown on 6H-SiC substrates by VLS mechanism using a Si-Ge melt. The photoluminescence and μ-Raman results show a clear and significant incorporation of germanium in the layers from the melt. A photoluminescence emission attributed to Ge related transitions is observed in the infrared region. μ-Raman spectra exhibit two peaks related to the Ge-Ge and Si-Ge bonds. From the characteristics of these Raman peaks, it was found that the amount of Ge incorporated inside the 3C layers increases with increasing Ge content of the melt. This has been verified by Particle-Induced X-rays Emission (PIXE) measurements which gave a Ge concentration varying from ~ 1x1019 to ~ 1x1020 at.cm-3. All these results suggest that Ge incorporates in the VLS grown 3C layers by forming Si-Ge-(C) nanoclusters.

Nonequilibrium Carrier Dynamics in DPB-Free 3C-SiC Layer Studied by Dynamic Grating Technique in Wide Excitation and Temperature Range

We applied picosecond dynamic grating technique for studies of carrier dynamics in ntype DPB(double positioning boundary)-free 3C-SiC (111) epilayer grown by VLS (vapour-liquidsolid) mechanism on 6H-SiC (0001). The measurements of bipolar diffusion coefficient D and carrier lifetime τR in the samples at various pump energies (0.5 – 3.0 mJ/cm2) and temperatures (9 – 300 K) provided the values of bipolar mobility of ~ 80 cm2/Vs and τR = 1.5 - 2.0 ns at 300 K. The ionized impurity scattering, dominant at T < 100 K, and carrier-density dependent lifetimes in 10- 300 K range were attributed to contribution of trapping centers which electrical activity saturates at high carrier density.

Single-domain 3C-SiC epitaxially grown on 6H-SiC by the VLS mechanism

Using the Vapor-Liquid-Solid mechanism in Ge-Si melts we have grown 3C-SiC layers on top of <0001>-oriented, Si face, 6H-SiC substrates. The surface morphology was free of spiral growth but highly step bunched. The 3C-SiC polytype was identified by micro- Raman spectroscopy and confirmed by low temperature photoluminescence. Electron backscattering diffraction mapping showed that the upper side of the layers is single-domain, i.e. that the 3C-SiC material displays only one in-plane orientation. Cross-sectional and planeview TEM investigations allowed detection of double positioning boundaries but only confined at the substrate/epilayer interface. The main additional defects found were stacking faults (SF) with a density of ~ 4.103 cm-1. Forming at the interface, they propagate through the epitaxial layer.