Mahta Haghi

The 90 nm Double-DICE storage element to reduce Single-Event upsets

In this paper, we introduce the Double-DICE storage element, which reduces charge sharing and collecting between the sensitive nodes of sensitive pairs in a Dual Interlocked Cell (DICE) storage cell in 90 nm technology. Interleaving two DICE storage cells in layout separates sensitive nodes by 8.5 µm, which is well beyond the minimum required of 5 µm shown in an earlier work. This reduces the probability of charge collecting in a sensitive pair in one DICE caused by a Single-Event strike. An area savings of 33.3 % results as compared to the case where no interleaving is used with the same nodal separation.

Single-event transient mitigation in sub-micron combinational circuits

In this paper we use a pair of cross-coupled inverters as a weak-latch to mitigate Single Event Transient (SET) effects in combinational logic for sub-micron technologies. A weak-latch is added to a sequential element input to slow down the data transitions and as a result filters out SET pulses that are faster than its delay. By applying this method we succeed to completely filter out transient pulse widths of up to 350 ps and to decrease SET pulse widths of up to 500 ps by more than 50%. SET pulse width measurements from 2-D TCAD simulations show that for 65-nm technology SET pulses induced by heavy ion particles with energies up to 14 MeV.cm2/mg can be completely filtered while SET pulses produced by particles with energies up to 20 MeV.cm2/mg are narrowed down by more than half of their original pulse width by using this weak-latch.

Experimental Demonstration of an Interference-Avoidance-Based Protocol for O-CDMA Networks

We demonstrate the transmission scheduling algorithm in an O-CDMA network to avoid congestion collapse in an O-CDMA network. Our result shows that transmission scheduling increases the performance of the system by orders of magnitude.

The effect of design parameters on single-event upset sensitivity of MOS current mode logic

In this paper, we describe and discuss the effects of design parameters such as transistor size, output voltage swing and bias current on radiation sensitivity of MOS current mode logic (MCML) type sequential elements that are used in high-speed communication systems. We have implemented latches and flip-flops in 90 nm technology and show how single-event upset can be mitigated just by adjusting particular design factors at the same clock frequency. It is shown that the critical charge needed to upset the logic state of a sequential element increases up to 5 times by increasing the bias current at the cost of more power and up to 2 times by increasing output voltage swing at the cost of more area. The effect of changing operation frequency from 500MHz to 4GHz on single-event upset is also investigated. For frequencies higher than 2 GHz, critical charge improves 1.3 times.

Increasing the bit rate in OCDMA systems using pulse position modulation techniques

We have experimentally demonstrated two novel pulse position modulation techniques, namely Double Pulse Position Modulation (2-PPM) and Differential Pulse Position Modulation (DPPM) in Time-Wavelength OCDMA systems that will operate at a higher bit rate compared to traditional OOK-OCDMA systems with the same bandwidth. With 2-PPM technique, the number of active users will be more than DPPM while their bit rate is almost the same. Both techniques provide variable quality of service in OCDMA networks.

Error-free data transmission through a tunable-bandwidth filter based on a MEMS-actuated microdisk resonator

System functionalities of matched filtering, channel banding, and wavelength demultiplexing are demonstrated using a unique MEMS-actuated microdisk resonator filter with dynamically tunable bandwidth. Error free operation of demultiplexed channel is realized.

A single-event upset hardening technique for high speed MOS Current Mode Logic

In this paper, we introduce a SEU-hard MOS Current Mode Logic (MCML) sequential element that is used in high speed communication systems. We have implemented latches and flip-flops in 65 nm technology and show that the critical charge needed to upset the sensitive nodes in these circuits is increased with this proposed design. Simulation has been conducted for clock rates of 0.5, 1, 2 and 4 GHz. The results show the critical charge increases more than 5 times (>440%) with this design while the delay (32 ps) is acceptable for GHz operations.

Experimental demonstration of interference avoidance protocol (transmission scheduling) in O-CDMA networks

We experimentally demonstrate a transmission scheduling algorithm to avoid congestion collapse in O-CDMA networks. Our result shows that transmission scheduling increases the performance of the system by orders of magnitude.

Experimental demonstration of code position modulation in an O-CDMA system to increase the number of users

A novel, code-position modulation(CPM) that permits increase in the number of active users proposed and experimentally demonstrated. CPM-O-CDMA system with 6-asynchronous users at bit-rate 2.5 Gb/s and BER<1E-9 demonstrated to increase the bit-rate by 4X.

Comparison of charge sharing reduction techniques in deep sub-micron CMOS processes

In this paper, we investigate and compare the effectiveness of different charge sharing techniques for reduction of charge sharing and collection among adjacent nodes in 65-nm technology NFET transistors. We use Synopsys 2-D TCAD mixed-mode simulations to measure collected charge at a node adjacent to a device struck by a heavy-ion particle for cases of using Shallow Trench Isolation (STI), Deep Trench Isolation (DTI), guard-ring and guard-diode; different nodal separations; and with particles of differing linear energy transfer (LET) strengths. The results show the most reduction in collected charge (more than 98%) at the adjacent node for DTI. Also, there is almost zero increase in area while using DTI; however, some pulse broadening at the struck node is observed.