Mahyar Shahsavari

Combining a volatile and nonvolatile memristor in artificial synapse to improve learning in Spiking Neural Networks

With the end of Moores law in sight, we need new computing architectures to satisfy the increasing demands of big data processing. Neuromorphic architectures are good candidates to low energy computing for recognition and classification tasks. We propose an event-based spiking neural network architecture based on artificial synapses. We introduce a novel synapse box that is able to forget and remember by inspiration from biological synapses. Two different volatile and nonvolatile memristor devices are combined in the synapse box. To evaluate the effectiveness of our proposal, we use system-level simulation in our Neural Network Scalable Spiking Simulator (N2S3) using the MNIST handwritten digit recognition dataset. The first results show better performance of our novel synapse than the traditional nonvolatile artificial synapses.

Efficient CNTFET-based design of quaternary logic gates and arithmetic circuits

A new voltage mode design is presented for quaternary logic using CNTFETs. This architecture with presentation of a new structure for voltage division can be applied on any four-valued logic implementation. To ensure the functionality of this promising proposed architecture, basic gates, half-adder, and full-adder are implemented using voltage divider. Moreover, a decoder is considered to enhance the parameters of half-adder such as power consumption, delay, and number of transistors. The designs are simulated using Hspice simulation tool. In comparison with prior works, our half-adder design is optimized by 75.2%, 7.8% and 77% in power consumption, delay and PDP parameters, respectively.

Parameter Exploration to Improve Performance of Memristor-Based Neuromorphic Architectures

The brain-inspired spiking neural network neuromorphic architecture offers a promising solution for a wide set of cognitive computation tasks at a very low power consumption. Due to the practical feasibility of hardware implementation, we present a memristor-based model of hardware spiking neural networks which we simulate with Neural Network Scalable Spiking Simulator (N2S3), our open source neuromorphic architecture simulator. Although Spiking neural networks are widely used in the community of computational neuroscience and neuromorphic computation, there is still a need for research on the methods to choose the optimum parameters for better recognition efficiency. With the help of our simulator, we analyze and evaluate the impact of different parameters such as number of neurons, STDP window, neuron threshold, distribution of input spikes, and memristor model parameters on the MNIST hand-written digit recognition problem. We show that a careful choice of a few parameters (number of neurons, kind of synapse, STDP window, and neuron threshold) can significantly improve the recognition rate on this benchmark (around 15 points of improvement for the number of neurons, a few points for the others) with a variability of four to five points of recognition rate due to the random initialization of the synaptic weights.

Towards an spiking deep belief network for face recognition application

Understanding brain mechanisms and its problem solving techniques is the motivation of many emerging brain inspired computation methods. In this paper, respecting deep architecture of the brain and spiking model of biological neural networks, we propose a spiking deep belief network to evaluate ability of the deep spiking neural networks in face recognition application on ORL dataset. To overcome the change of using spiking neural networks in a deep learning algorithm, Siegert model is utilized as an abstract neuron model. Although there are state of the art classic machine learning algorithms for face detection, this work is mainly focused on demonstrating capabilities of brain inspired models in this era, which can be serious candidate for future hardware oriented deep learning implementations. Accordingly, the proposed model, because of using leaky integrate-and-fire neuron model, is compatible to be used in efficient neuromorphic platforms for accelerators and hardware implementation.