Mahzad Azarmehr

Low-power oscillator for passive radio frequency identification transponders

Passive radio frequency identification tags extract energy from incoming electromagnetic waves to power up their internal circuitry. Such a limited source of power demands efficient circuits to minimise the power consumption. In this work a new technique is proposed to design a low-power ring oscillator in which the voltage swing of internal nodes are constrained to lower the dynamic power consumption. The proposed power reduction technique can be employed for RFID tags operating over different frequency bands from low frequency (LF) to microwave. A low-power oscillator operating in the medium-frequency range (6–16 MHz) for applications such as electronic article surveillance and item management has been implemented in this work. Post-layout simulation results using STMicroelectronics CMOS 65 nm technology indicate that the proposed method can reduce the power consumption by more than 25%.

Low-Power Finite Impulse Response (FIR) Filter Design Using Two-Dimensional Logarithmic Number System (2DLNS) Representations

In most real-time DSP applications, high performance is a prime target. Here, performance may be interpreted as a combination of higher speed, lower power consumption, sufficient precision, and VLSI area efficiency. It has been experienced that efficient digital multiplication is a prerequisite for high-speed DSP applications. The MDLNS, which has similar properties to the classical LNS, is an alternative approach to conventional number systems for performing multiplication, through using parallel small adders. In addition, by applying recursive multiplication scheme, larger word length multiplication can be performed by use of several small multipliers. The concept of recursive multiplication can be applied to 2DLNS structures, resulting in more efficient digital multipliers. In this work, the recursive 2DLNS-based multipliers have been applied to FIR filter design. These applications demonstrate the superiority of our architectures in terms of VLSI area and power consumption.

A two-dimensional logarithmic number system (2DLNS)-based Finite Impulse Response (FIR) filter design

The ever increasing demand for low power DSP applications has directed researchers to contemplate a variety of potential approaches in different contexts. In this regard, using some alternative number systems, which inherently are capable of reducing the hardware complexity, have been propounded. In this work, a 2DLNS-based platform for multiplication intensive DSP applications is presented. Implementing an FIR filter structure on this basis shows outstanding privilege to its binary counterpart in terms of VLSI area and power consumption.

High-speed CMOS track-and-hold with an offset cancellation replica circuit

The trade-off between pedestal error and acquisition time limits the level of speed-accuracy that can be achieved by CMOS track-and-hold circuits. This paper presents a circuit technique to design a high-resolution, high-speed T/H circuit. The sampling error produced by clock feedthrough and the charge injection of CMOS switches are eliminated through a cancellation technique using a replica circuit. Simulation results using CMOS 90nm process confirm that the proposed method lowers the pedestal error considerably and supports linearity over 9.8 effective bits at 500MHz sampling rate for input signals up to 10MHz.

Recursive architectures for 2DLNS multiplication

In the area of signal processing, digital circuits are advantageous in terms of lower sensitivity to noise and process variations, simplicity of design, programmability and test, while they attain higher speed, more functionality per chip, lower power dissipation or lower cost. Since some of DSP algorithms heavily rely on multiplication, there are constant demands for more efficient multiplication structures. In this paper, 2DLNS-based multiplication architectures with two different levels of recursion are presented. Our architectures combine some of the flexibility of software with the high performance of hardware through implementing the recursive multiplication schemes on a 2DLNS processing structure. The implementations demonstrate the efficiency of 2DLNS in DSP applications and show outstanding results in terms of operation delay and dynamic power consumption.

A Simple Central Processing Unit with Multi-Dimensional Logarithmic Number System Extensions

For implementing modern and massively parallel multiplication intensive DSP applications, novel solutions such as Multidimensional Logarithmic Number System (MDLNS) have been considered. In the MDLNS, Similar to the Logarithmic Number System (LNS), some of the operations such as multiplication and division are performed rather easily. The calculation over different bases and digits are completely independent and the logarithmic properties of the MDLNS allow for a reduced complexity multiplication. The use of more than one base facilitates more precise mapping of binary data and leads to dramatic reduction in size of the exponents, and consequently to hardware savings.

Secure authentication and access mechanism for IoT wireless sensors

Security is the main challenge in the design and implementation of todays ubiquitous interconnected objects on the Internet network infrastructure. Many security solutions have been already proposed to address security concerns for IoT enabled devices. In this paper, an integrated approach for authentication and access control is presented for communication with wireless sensor nodes in IoT networks. The proposed method provides strong protection against known attacks such as energy exhausting, and Man-In-The-Middle.

A RISC architecture for 2DLNS-based signal processing

The multi-dimensional logarithmic number system (MDLNS) provides a reduction in the size of the number representation and promises a lower cost realisation of arithmetic operations. The non-linear nature of the representation and independency of the parallel-based computations combined with multi-digit extensions of the MDLNS representations along with simplified arithmetic operations, make MDLNS suitable for some multiplication intensive DSP applications. The work presented in this paper is the design and implementation of a 2DLNS-based processor architecture. This CPU takes advantage of a relatively simple architecture and a well designed organisation which greatly improves the implementation of many DSP algorithms. An assembly programme is also written to implement a 2DLNS-based filterbank architecture. This implementation demonstrates the efficiency and ease of use of 2DLNS CPU in real applications.