Mai Phi Hung

Highly stable fluorine-passivated In–Ga–Zn–O thin-film transistors under positive gate bias and temperature stress

A highly stable fluorine-passivated In–Ga–Zn–O (IGZO) thin-film transistor (TFT) was demonstrated under positive gate bias and temperature stress (PBTS). The defects in the IGZO TFT were passivated by fluorine, which was introduced into a SiOx etching stopper during the deposition of fluorinated silicon nitride for passivation and diffused during post-fabrication annealing. From the results of secondary ion mass spectrometry analysis, the reliability of the IGZO TFT under PBTS was observed to be markedly improved even at a stress temperature of 100 °C when fluorine diffusion was detected in the IGZO channel. The fluorine-passivated IGZO TFT has improved operation temperature and is advantageous for achieving high-performance and high-reliability oxide TFTs for next-generation displays.

Suppression of Degradation Induced by Negative Gate Bias and Illumination Stress in Amorphous InGaZnO Thin-Film Transistors by Applying Negative Drain Bias

The effect of drain bias (V(DS)) on the negative gate bias and illumination stress (NBIS) stability of amorphous InGaZnO (a-IGZO) thin-film transistors was investigated using a double-sweeping gate voltage (V(GS)) mode. The variation in the transfer characteristics was explored using current-voltage and capacitance-voltage characteristics. In the initial stage (<1000 s) of NBIS with grounded V(DS) (V(GS) = -40 V and V(DS) = 0 V), the transfer characteristics shifted negatively with an insignificant change in the subthreshold swing (SS) because of hole trapping at an IGZO/gate insulator interface. On the other hand, on-current degradation was observed and was accelerated in the forward measurement as the NBIS duration increased. The results indicated that NBIS induced donor-like defects near the conduction band; however, the transfer curves in the reverse measurement shifted positively without on-current and SS degradations. It was found that the degradations were enhanced by applying a positive V(DS) bias (V(GS) = -40 V and V(DS) = 40 V); in contrast, they could be reduced by applying a small negative V(DS) of V(DS) > V(GS) (V(GS) = -40 V and V(DS) = -20 V). Furthermore, it was confirmed that the NBIS degradations could be suppressed by applying a large negative V(DS) bias of V(DS) < V(GS) (V(GS) = -40 V and V(DS) = -60 V) during NBIS.

Investigating Effect of Postannealing Time on Positive Bias Stress Stability of In–Ga–Zn–O TFT by Conductance Method

The conductance method was used to investigate the positive bias stress (PBS) degradation mechanism of In-Ga-Zn-O (IGZO) thin-film transistor (TFT). The effects of postannealing time on the PBS degradation mechanism were investigated. The stabilization of the donorlike interface defects was found to be the reason for the threshold voltage instability in the IGZO-TFT under the PBS test. The donorlike defects at the front channel interface and in the plasma-enhanced chemical vapor deposition (PE-CVD) SiOx acted as the electron trapping centers. The electron trapping resistance of the PE-CVD SiOx was improved by increasing the postannealing time, resulting in an improvement in the PBS stability. However, long-time postannealing-induced creation of the deep acceptorlike interface defects in the TFT under the PBS. The energy distribution of the created deep acceptorlike interface defects was revealed using the conductance measurement.