Tatsuya Toda

Electrical Properties of the Thin-Film Transistor With an Indium–Gallium–Zinc Oxide Channel and an Aluminium Oxide Gate Dielectric Stack Formed by Solution-Based Atmospheric Pressure Deposition

We developed a thin-film transistor (TFT) with an amorphous-indium-gallium-zinc oxide (IGZO) channel and aluminium oxide (AlO_x) gate dielectric stack that was formed using a solution-based atmospheric pressure chemical vapor deposition. A breakdown electric field of 5.9 MV/cm and a dielectric constant of 6.8 were achieved for the AlO_x gate dielectric. The nonvacuum-processed IGZO TFT gave a field-effect mobility of 4.2 cm² · V^-1 · s^-1 and an on/off current ratio of over 10⁸. Moreover, the proposed deposition method is a powerful tool for material research to explore multicomponent oxide insulators and semiconductors.

Highly stable fluorine-passivated In–Ga–Zn–O thin-film transistors under positive gate bias and temperature stress

A highly stable fluorine-passivated In–Ga–Zn–O (IGZO) thin-film transistor (TFT) was demonstrated under positive gate bias and temperature stress (PBTS). The defects in the IGZO TFT were passivated by fluorine, which was introduced into a SiOx etching stopper during the deposition of fluorinated silicon nitride for passivation and diffused during post-fabrication annealing. From the results of secondary ion mass spectrometry analysis, the reliability of the IGZO TFT under PBTS was observed to be markedly improved even at a stress temperature of 100 °C when fluorine diffusion was detected in the IGZO channel. The fluorine-passivated IGZO TFT has improved operation temperature and is advantageous for achieving high-performance and high-reliability oxide TFTs for next-generation displays.

Suppression of Degradation Induced by Negative Gate Bias and Illumination Stress in Amorphous InGaZnO Thin-Film Transistors by Applying Negative Drain Bias

The effect of drain bias (V(DS)) on the negative gate bias and illumination stress (NBIS) stability of amorphous InGaZnO (a-IGZO) thin-film transistors was investigated using a double-sweeping gate voltage (V(GS)) mode. The variation in the transfer characteristics was explored using current-voltage and capacitance-voltage characteristics. In the initial stage (<1000 s) of NBIS with grounded V(DS) (V(GS) = -40 V and V(DS) = 0 V), the transfer characteristics shifted negatively with an insignificant change in the subthreshold swing (SS) because of hole trapping at an IGZO/gate insulator interface. On the other hand, on-current degradation was observed and was accelerated in the forward measurement as the NBIS duration increased. The results indicated that NBIS induced donor-like defects near the conduction band; however, the transfer curves in the reverse measurement shifted positively without on-current and SS degradations. It was found that the degradations were enhanced by applying a positive V(DS) bias (V(GS) = -40 V and V(DS) = 40 V); in contrast, they could be reduced by applying a small negative V(DS) of V(DS) > V(GS) (V(GS) = -40 V and V(DS) = -20 V). Furthermore, it was confirmed that the NBIS degradations could be suppressed by applying a large negative V(DS) bias of V(DS) < V(GS) (V(GS) = -40 V and V(DS) = -60 V) during NBIS.

Effect of drain bias on negative gate bias and illumination stress induced degradation in amorphous InGaZnO thin-film transistors

The effect of drain bias on negative gate bias and illumination stress (NBIS) stability of a-IGZO TFTs was investigated. The evolutions of transfer curves were explored with NBIS time using current-voltage characteristics measurements. In the initial stage (<;1000 s) of NBIS with grounded VDS, transfer curves shifted negatively without subthreshold swing (S) degradation due to hole-trapping at the IGZO/gate insulator interface. On the other hand, on-current degradation occurred and was enhanced as NBIS duration increased. Results indicated that NBIS-induced defects were created above Fermi level energy (EF). NBIS-induced states creation was enhanced under NBIS with positive drain bias (VDS) of 40 V; however, it was found that NBIS-induced defects can be suppressed under negative VDS bias of -60 V.

High-Performance Top-Gate and Self-Aligned In–Ga–Zn-O Thin-Film Transistor Using Coatable Organic Insulators Fabricated at 150 °C

We fabricated top-gate and self-aligned indium- gallium-zinc-oxide thin-film transistors (IGZO TFTs) at a maximum process temperature of 150 °C using a coatable organic gate insulator (OGI). By forming a damage and contaminationfree interface between the IGZO channel and OGI, and forming low-resistive source/drain regions by Al reaction method, we achieved good TFT properties, such as field effect mobility of 9.8 cm2/Vs, subthreshold swing of 0.21 V/decade, and hysteresis of 0.3 V, with minimizing a parasitic capacitance. Although the TFT showed an abnormal degradation behavior under positive gate bias stress testing in an ambient air, it was suppressed by forming an additional organic passivation layer.

Anomalous Increase in Field-Effect Mobility in In–Ga–Zn–O Thin-Film Transistors Caused by Dry-Etching Damage Through Etch-Stop Layer

The influence of dry-etching (D/E) damage during the source/drain (S/D) electrode etching process on the electrical properties of a bottom-gate In-Ga-Zn-O thin-film transistor (TFT) was investigated by varying the thickness of the etch-stop layer (ESL). For a thicker ESL of 200 nm, electrical properties of the TFTs with S/D electrodes formed by dry and wet-etching were comparable. However, an anomalous increase in apparent field-effect mobility (μFE) was observed from the TFT with the S/D-D/E process with thinner ESL. Experimental and device simulation results clarified that the current flow line in the channel and an effective channel length were strongly influenced by the carrier density of the low-resistive region formed at a back-channel region, which was induced by the S/D-D/E damage through ESL.

Thin-Film Transistors Using Uniform and Well-Aligned Single-Walled Carbon Nanotubes Channels by Dielectrophoretic Assembly

A single-walled carbon nanotube thin-film transistor (SWCNT TFT) was formed by an aligned SWCNTs channel assembled by the dielectrophoretic (DEP) process. In this work, we investigated the effects of the DEP factors (frequency, solution concentration) on structural (orientation and density in the SWCNT channels) and electrical properties of SWCNT TFTs. A uniform, well-aligned and density controlled SWCNT channel was achieved by optimizing the DEP assembly process, and as a result, electrical properties (mobility and on/off current ratio) of SWCNT TFTs were improved. In addition, we also discussed the effect of uniformity of assembled SWNTs in a channel on performance variation of the SWCNT TFTs. We found that the tube density and uniformity are key parameters which determine electrical properties and performance variation of SWCNT TFTs.