Makarem A. Hussein

Materials' impact on interconnect process technology and reliability

We explain how the manufacturing technology and reliability for advanced interconnects is impacted by the choice of metallization and interlayer dielectric (ILD) materials. The replacement of aluminum alloys by copper, as the metal of choice at the 130-nm technology node, mandated notable changes in integration, metallization, and patterning technologies. Those changes directly impacted the reliability performance of the interconnect system. Although further improvement in interconnect performance is being pursued through utilizing progressively lower dielectric constant (low-k) ILD materials from one technology node to another, the inherent weak mechanical strength of low-k ILDs and the potential for degradation in the dielectric constant during processing pose serious challenges to the implementation of such materials in high-volume manufacturing. We consider the cases of two ILD materials, carbon-doped silicon dioxide and low-k spin-on-polymer, to illustrate the impact of the ILD choice on the process technology and reliability of copper interconnects.

A novel approach to dual damascene patterning

In this paper, we present and discuss a novel approach to dual damascene patterning based on the invention of SLAM (Sacrificial Light Absorbing Material). We will focus on dual damascene patterning problems that led to the invention of SLAM, and present a side-by-side comparison of the patterning performance of SLAM-assisted dual damascene patterning and a Bottom Anti-Reflective Coating (BARC), the industrys primary approach. SLAM-assisted dual damascene patterning is an enabling technology for Intels 130 nm technology and beyond.

Particle control in dielectric etch chamber

A methodology for evaluating and controlling particle performance in a dielectric etch system is developed and presented. Analysis of particle samples, collected from premature chamber failures for out-of-control particle levels, suggests sputtering of the upper electrode during etching is a key modulator to this problem. To eliminate such sputtering, we designed a series of experiments with the objective of identifying a between-lot conditioning (BLC) process capable of creating a uniform and solid layer of polymer coating that covers the entire upper electrode of a parallel plate, RF, magnetically enhanced reactive ion etch system. An approach comprising a series of short wafer processing marathon runs, with polymer coverage and particle performance as the two main responses, was then used to identify a candidate process for BLC recipe and usage frequency. Adequate non flaking polymer coverage of the upper electrode was achieved by utilizing a BLC process based on octafluoro-cyclobutane/oxygen/argon/carbonmonoxide [C/sub 4/F/sub 8//O/sub 2//Ar/CO] chemistry at high RF power and short transit time settings. The candidate process was then optimized and tested in a manufacturing pilot involving multiple production etch chambers and was subjected to extensive process performance metrics. Based on this methodology, the optimized BLC was successful in controlling defects and in attaining the mean wafer between wet clean goal for the etch system under investigation.

Dual damascene patterning of polymer interlayer dielectrics

We unveil an innovative and manufacturable process technique to pattern dual damascene structures in polymer interlayer dielectric (ILD) without the need for either a permanent hardmask or an embedded etch stop (ES) layer. We introduce a sacrificial hardmask (SAM) and a sacrificial via fill (SAVIL) material to enable the patterning process. Since the hardmask is sacrificial, it is removed at the end of the patterning process without compromising the overall dielectric value of the ILD. The utilization of the SAVIL material provided the trench lithography step with a hole-free, and planar substrate. We demonstrate patterning of dual damascene structures using SAM/SAVIL in a via-first integration scheme through a comparative patterning performance between the SAM/SAVIL-assisted dual damascene patterning and the dual hardmask approach used most in the industry.