Peter K. Moon

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.

Development of Cu etch process for advanced Cu interconnects

Recent development efforts in copper etch processing show promising results in many areas that have posed significant challenges for this new technology. We report on etch performance for features down to 0.25 /spl mu/m with aspect ratios greater than 2:1. Copper etch rates greater than 5000 /spl square//min have been achieved, and corrosion-free post Cu etch performance has been demonstrated for periods in excess of 72 hours. Electrical tests were conducted and are presented in detail.

Process roadmap and challenges for metal barriers [copper interconnects]

Copper interconnects require two types of barrier layers: a liner on the sides and bottoms of the damascene features and a cap on top of the damascene features. The key functions of the barrier layers are to prevent copper and oxygen diffusion and promote adhesion with both the interlayer dielectric (ILD) and the copper. The cap layer must also protect the copper from corrosion during subsequent patterning steps and act as an etchstop for partially landed vias. Most copper damascene processes use a PVD Ta and/or Ta(N) alloy liner and PECVD SiN or SiCN dielectric cap. However, as copper interconnects continue to scale to finer dimensions these metal barrier technologies become problematic due to wiring resistance and current density issues. This paper describes some of the alternative liner and cap technologies that are being developed to address these issues.

High volume manufacturing issues for on-die interconnects at the 45nm process node

High volume manufacturing (HVM) for silicon devices poses numerous challenges beyond simply designing and demonstrating a useful product. This paper describes several of those challenges using examples from Intels HVM experience fabricating on-die interconnects for high performance logic products at the 45nm process node.