Makoto Amamiya

An Adaptive Agent Oriented Software Architecture

Method and agent network architecture for processing a subject message, where each agent has a view of its own domain of responsibility. An initiator agent which receives a user-input request and does not itself have a relevant interpretation policy, queries its downchain agents whether the queried agent considers such message to be in its domain of responsibility. Each queried agent recursively determines whether it has an interpretation policy of its own that applies to the request, and if not, further queries its own further downchain neighboring agents. The further agents eventually respond to such further queries, thereby allowing the first-queried agents to respond to the initiator agent. The recursive invocation of this procedure ultimately determines one or more paths through the network from the initiator agent to one more more leaf agents. The request is then transmitted down the path(s), with each agent along the way taking any local action thereon and passing the message on to the next agent in the path. In the event of a contradiction, the network is often able to resolve many of such contradictions according to predetermined algorithms. If it cannot resolve a contradiction automatically, it learns new interpretation policies necessary to interpret the subject message properly. Such learning preferably includes interaction with the user (but only to the extent necessary), and preferably localizes the learning close to the correct leaf agent in the network.

Fine-grain multi-thread processor architecture for massively parallel processing

Latency, caused by remote memory access and remote procedure call, is one of the most serious problems in massively parallel computers. In order to eliminate the processors idle time caused by these latencies, processors must perform fast context switching among fine-grain concurrent processes. In this paper, we propose a processor architecture, called Datarol-II, that promotes efficient fine-grain multi-thread execution by performing fast context switching among fine-grain concurrent processes. In the Datarol-II processor, an implicit register load/store mechanism is embedded in the execution pipeline in order to reduce memory access overhead caused by context switching. In order to reduce local memory access latency, a two-level hierarchical memory system and a load control mechanism are also introduced. We describe the Datarol-II processor architecture, and show its evaluation results.<<ETX>>

Adaptive exploiting user profile and interpretation policy for searching and browsing the Web on KODAMA system

The main thrust of the KODAMA research project is an investigation into novel ways of agentifying the Web based on the pre-existing hyper-link structure, and how this community of agents can automatically achieve and update its interpretation policies and cooperate with other agents to retrieve online distributed relevant information on the Web. The paper focuses on the use of the user interface agents in the KODAMA system for personalized information filtering and adapting, and discusses the method to update a user profile and interpretation policies adaptively for the user. This is an ideal and challenging environment for interface agents. The proposed idea is to employ an adaptive autonomous user interface agent that works for satisfying a users information needs cooperatively with other agents in the KODAMA system, Web page agents and server agents.

KUMP/D: the Kyushu University multi-media processor

High speed image and video processing is a key technology in multimedia applications, and, therefore, currently, many hardware accelerators to speed up such processing are developed and used. However, for the next generation advanced multimedia applications in the next generation, such as high quality virtual reality, bidirectional visual interface, etc., the hardware accelerators can not deal with tasks involved in these applications. This is because these tasks consist of complex and irregular computation structures, and therefore, it is not easy to implement simple hardware accelerators for these tasks. Considering the above situation, for the next generation multimedia applications, we have been developing a MIMD based multimedia processor, KUMP/D (Kyushu University Multimedia Processor on Datarol-II). KUMP/D is a flexible parallel processor, based on fine grain parallel processing, which is which indispensable in complex and irregular computation, and is also equipped with a specialized I/O network. This I/O network has enough throughput for real time video I/O, providing a mechanism, which supports the synchronization of process executions and real time video frames.

A dataflow language with object-based extension and its implementation on a commercially available parallel machine

We propose a massively parallel programming language, called “V,” which would minimize the difficulties in writing massively parallel programs. To abstract away the timing problem in writing parallelaway the timing problem in writing parallel programs, we based our work on a dataflow-based functional programming language. Then, we extended the base language with an object-based abstraction, called “agent,” to write parallel entities which contain their own states and can communicate with each other. In addition to connecting agents explicitly, an abstraction of ensembles of agents on a predefine topology descrip tion, called “field,” is introduced in order to write a massively parallel program which naturally reflects the structure of a problem. In this paper, we also discuss the implementation of V, including a preliminary evaluation, on a commercially available distributed-memory parallel machine, Fujitsu AP1OOO. Although it is easy to extract parallelism at various levels, including finegrained parallelism, from V programs, it is difficult to run V programs efficient 1y on stock parallel machines. Nevertheless, we tried to implement V on a stock parallel machine, since our aim is to develop a language that would be practical, not only on special fine-grained machines, but also stock machines.

Datarol: a parallel machine architecture for fine-grain multithreading

We discuss a design principle of massively parallel distributed-memory multiprocessor architecture which solves latency problem, and present the Datarol machine architecture. Latencies, caused by remote memory access and remote procedure call, are most serious problems in massively parallel computers. In order to eliminate the processor idle times caused by these latencies, processors must perform fast context switching among fine-grain concurrent processes. First, we present a processor architecture, called Datarol-II, that promotes efficient fine-grain multithread execution by performing fast context switching among fine-grain concurrent processes. In the Datarol-II processor, an implicit register load/store mechanism is embedded in the execution pipeline in order to reduce memory access overhead caused by context switching. In order to reduce local memory access latency, a two-level hierarchical memory system and a load control mechanism are also introduced. Then, we present a cost-effective design of the Datarol-II processor, which incorporates off-the-shelf high-end microprocessor while preserving the fine-grain dataflow concept. The off-the-shelf microprocessor Pentium is used for its core processing, and a co-processor called FMP (Fine-grain Message Processor) is designed for fine grained message handling and communication controls. The co-processor FMP is designed on the basis of FMD (Fine-grain Message Driven) execution model, in which fine-grain multi-threaded execution is driven and controlled by simple fine-grain message communications.

Hybrid Approach for Non-strict Dataflow Program on Commodity Machine

Dataflow-based non-strict functional programming languages have attractive features for writing concise programs. In order to avoid performance penalties on non-dataflow stock machines, we speculatively use a stack frame instead of a heap frame for a fine grain function instance, which may require dynamic scheduling. As a static approach, we introduce a merging policy to a thread partitioning algorithm in order to find functions with a potentially strict call interface. To complement this static analysis, we provide a hybrid runtime mechanism which can dynamically change a suspended stack frame into a heap frame. The results of the performance evaluation indicate that we can reduce superfluous heap frame management and achieve practical performance even on stock machines.

Co-processor System Design for Fine-Grain Message Handling in KUMP/D

In parallel processing, fine-grain parallel processing is quite effective solution for latency problem caused by remote memory accesses and remote procedure calls. We have proposed a processor architecture, called Datarol-II, that promotes efficient fine-grain multi-thread execution by performing fast context switching among fine-grain concurrent processes. We are now building a prototype multi-media machine KUMP/D (Kyushu University Multi-media Processor on Datarol-II) on the basis of the fine-grain multi-threading architecture. In the design of the KUMP/D, we used the commercial microprocessor for its processing element, and designed a co-processor, called FMP(Fine-grain Message Processor), for fine-grain message handling and communication control. In this paper, we show the KUMP/D processor design and its performance evaluation.

Datarol-II: A Fine-Grain Massively Parallel Architecture

In this paper, we introduce the Datarol-II processor, that can efficiently execute a fine-grain multi-thread program, called Datarol. In order to achieve the efficient multi-thread execution by reducing context switching overhead, we introduce an implicit register load/store mechanism in the execution pipeline. A two-level hierarchical memory system is also introduced in order to reduce memory access latency. The simulation results show that the Datarol-II processor can tolerate remote memory access latencies and execute a fine-grain multi-thread program efficiently.

Reducing overhead in implementing fine-grain parallel data-structures of a dataflow language on off-the-shelf distributed-memory parallel computers

In order to show the feasibility of a fine-grain dataflow computation scheme, we are implementing a fine-grain dataflow language on off-the-shelf computers, using a fine-grain multithread approach. Fine-grain parallel data-structures such as I-structures provide high level abstraction to easily write programs with potentially high parallelism. The results of preliminary experiments on a distributed memory parallel machine indicate that the performance inefficiency related to fine-grain parallel data-structures in the naive implementation is mainly caused by the calculation of the local address for distributed data, and the frequent fine-grain data access using message passing. In order to reduce the addressing overhead, we introduce a two-level table addressing technique. We employ a caching mechanism and a grouping mechanism for the fine-grain data access. The preliminary performance evaluation results indicate that these techniques are effective to improve the performance.