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Development of a Thread Scheduler for Global Aggregation of Sibling Threads

Chip-level multiprocessors (CMP) have multiple processing cores (Cores) and generally have their cache shared by each Core. On CMP, the combination of threads running simultaneously on different Cores as well as the order of threads running on one Core influences the utilization of the cache. We consider that an OS level thread scheduler for concurrent and parallel thread execution is the key to utilize the cache and reduce the memory accesses. Previously, we have developed a thread scheduler which recognizes the memory address space of each thread for concurrent execution and investigated its effect on a single processor environment. In this paper, we demonstrate the extension of our previous scheduler for parallel execution on CMP. Our scheduler is composed of the independent schedulers per Core and is able to let them cooperate with little cost. According to our investigation with Sysbench benchmark, this extension enhances the effect of our previous scheduler and results in the more reduction of the execution time.