Tetsuo Kawano

Processor and pipeline reconfiguration control method

Semiconductor device having an arithmetic unit of a reconfigurable circuit configuration in accordance with stored configuration data and a memory storing fixed value data to be supplied to the arithmetic unit, requiring no data area for storing fixed value data to be set in a configuration memory

Reconfigurable operation apparatus

Timing analysis apparatus, timing analysis method and program product

Method and program for designing semiconductor integrated circuits to optimize clock skews on plurality of clock paths

Reconfigurable processor and semiconductor device

Reconfigurable address generation circuit for image processing, and reconfigurable LSI comprising the same

Semiconductor integrated circuit timing analysis apparatus timing analysis method and timing analysis program

Operation apparatus, operation apparatus control method, program and computer readable information recording medium

Array processor having reconfigurable data transfer capabilities