Makoto Ueda

System-On-a-Chip mixed bus architecture

TRANSPARENT LATCH CIRCUIT

CACHE COHERENCY CONTROL METHOD, SYSTEM, AND PROGRAM

Process tolerant delay circuit

Process tolerant delay circuit having process sensitive and process insensitive components placed therein

System having cache snoop interface independent of system bus interface

Multiprocessor system and exclusive control method therein

Multiprocessor system, processor module for use therein, and task allocation method in multiprocessing

Processor module for a multiprocessor system and task allocation method thereof

DRAM access method and a DRAM controller using the same