Alan J. Drake

A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor

A distributed critical-path timing monitor (CPM) is designed as part of the POWER6trade microprocessor in 65nm SOI. The CPM is capable of monitoring timing margin, process variation, localized noise and VDD droop, or clock stability. It tracks critical-path delay to within 3 FO2 delays at extreme operating voltages with a standard deviation less than frac12 an FO2 delay. The CPM detects DC VDD droops greater than 10mV and tracks timing changes greater than 1 FO2 delay.

Resonant clocking using distributed parasitic capacitance

A resonant-clock generation and distribution scheme that uses the inherent, parasitic capacitance of the clocked logic as a lumped capacitor in a negative-resistance oscillator is described. Clock energy is resonated between inductors and the parasitic, local clock network to save power over traditional clocking methodologies. Theory predicts that the data passing though the clocked logic will change the clock frequency by less than 1.25%. A resonant clock test chip was designed and fabricated in an IBM 0.13-/spl mu/m partially depleted SOI process. Although the test chip was designed to operate in the gigahertz range using integrated inductors, startup difficulties required the addition of external inductance to reduce the resonant frequency so that the effects of the parasitic capacitance could be measured. The parasitic capacitance is approximately 40 pF per clock phase, resulting in a clock frequency between 106 and 146 MHz, depending on biasing. At its most efficient bias point, the clock dissipated 2.09 mW, which is approximately 35% less power than a conventional, buffer-driven clock. The maximum period jitter measured in the resonant clock due to changing data in the clocked latches was 55 ps at 124 MHz, or 0.68% of the clock period.

Active management of timing guardband to save energy in POWER7

Microprocessor voltage levels include substantial margin to deal with process variation, system power supply variation, workload induced thermal and voltage variation, aging, random uncertainty, and test inaccuracy. This margin allows the microprocessor to operate correctly during worst-case conditions, but during typical conditions it is larger than necessary and wastes energy. We present a mechanism that reduces excess voltage margin by (1) introducing a critical path monitor (CPM) circuit that measures available timing margin in real-time, (2) coupling the CPM output to the clock generation circuit to adjust clock frequency within cycles in response to excess or inadequate timing margin, and (3) adjusting the processor voltage level periodically in firmware to achieve a specified average clock frequency target. We implemented this mechanism in a prototype IBM POWER7 server. During better-than-worst case conditions our guardband management mechanism reduces the average voltage setting 137–152 mV below nominal, resulting in average processor power reduction of 24% with no performance loss while running industry-standard benchmarks.

Introducing the Adaptive Energy Management Features of the Power7 Chip

Power7 implements several new adaptive power management techniques which, in concert with the EnergyScale firmware, let it proactively exploit variations in workload, environmental conditions, and overall system use to meet customer-directed power and performance goals. These innovative features include per-core frequency scaling with available autonomic frequency control, per-chip automated voltage slewing, power consumption estimation, and hardware instrumentation assist.

Active Guardband Management in Power7+ to Save Energy and Maintain Reliability

Microprocessor voltage levels traditionally include substantial margin to ensure reliable operation despite variations in manufacturing, workload, and environmental parameters. This margin allows the microprocessor to function correctly during worst-case conditions, but during typical operation it is larger than necessary and wastes energy. The authors present a mechanism that reduces excess voltage margin by introducing a critical-path monitor (CPM) circuit that measures available timing margin in real time; coupling the CPM output to the clock generation circuit to rapidly adjust clock frequency in response to excess or inadequate timing margin; and adjusting the processor voltage level periodically in firmware to achieve a specified average clock frequency target. They first demonstrated this mechanism in an IBM Power7 server and proved its effectiveness in the Power7+ product. Power consumption on the VDD rail was reduced by 11 percent for SPEC CPU2006 workloads with negligible performance loss yet increased protection against noise events.

Dynamic measurement of critical-path timing

A high bandwidth critical path monitor (1 sample/ cycle at 4-5 GHz) capable of providing real-time timing margin information to a variable voltage/frequency scaling control loop is described. The critical path monitor tracks the critical path delay to within 1 FO2 inverter delay with a standard deviation less than 3 FO2 delays over process, voltage, temperature, and workload. The CPM is sensitive to 20 mV/bit A/C and 10 mV/bit DC voltage changes, and less than 10degC/bit temperature changes.

A microprocessor design project in an introductory VLSI course

An introductory very large scale integration (VLSI) design course has been taught at the University of Michigan (USA) since 1980. In 1990, it was redesigned around a simple 8-bit microprocessor project in the format described in this paper; in 1996, the project was updated to a 16 bit reduced instruction set computer (RISC) processor. The authors describe the course philosophy, content, and the baseline architecture from which class projects begin. The key features of the course are: close coordination of lectures and project activity; prompt and regular feedback on design work; and a schedule which spreads the workload over the full term. In this course, students learn VLSI fundamentals and good design methodology that will be important throughout their careers.

4.0GHz 0.18/spl mu/m CMOS PLL based on an interpolate oscillator

Phase-locked loops (PLLs) have not been the bottleneck in processor frequency performance. However, new digital circuit families, architectural improvements, and deeper pipelines have challenged this trend. In this paper, we present two novel interpolative oscillators and a phase-locked loop which is capable of clocking even the most demanding logic families. Experimental results, from a TSMC 0.18/spl mu/m process, show oscillator frequencies as high as 4.6GHz and rms jitter values of less then 1.25ps. Additionally, the PLL was able to lock to form a 4GHz output signal. These results are among the best published to date in this process.

Single-cycle, pulse-shaped critical path monitor in the POWER7+ microprocessor

A 32nm SOI critical path monitor (CPM) that can provide timing measurements to a Digital PLL for dynamic frequency adjustments in the 8-core POWER7+™ microprocessor is described. The CPM calibrates to within 2% of cycle time from nominal to turbo voltages. Its voltage sensitivity is 10mV/bit. It tracks processor temperature sensitivity to within 1.5% of nominal frequency, and has a sample jitter less than 1.5% of nominal frequency. The ability to detect noise dynamically allows the system to operate the processor closer to its optimal frequency for any given voltage, resulting in lower voltage for power savings or higher frequency for performance improvements.

Voltage droop reduction using throttling controlled by timing margin feedback

An active processor throttling control loop using critical path timing measurements is enabled in the shipping POWER7™ based P775 supercomputer to prevent voltage droop induced failures. As a result, worst-case workload-induced voltage droop events are reduced by more than 50% compared to the system operating without the control loop. The reduction in operating voltage afforded by this technique translates to significant yield improvement, reduced failure rates, and improved power efficiency.