Mamidala Jagadesh Kumar

A new dual-material double-gate (DMDG) nanoscale SOI MOSFET-two-dimensional analytical modeling and simulation

In this paper, we present the unique features exhibited by a modified asymmetrical double-gate (DG) silicon-on-insulator (SOI) MOSFET. The proposed structure is similar to that of the asymmetrical DG SOI MOSFET with the exception that the front gate consists of two materials. The resulting modified structure, i.e., a dual-material double-gate (DMDG) SOI MOSFET, exhibits significantly reduced short-channel effects (SCEs) when compared with the DG SOI MOSFET. SCEs in this structure have been studied by developing an analytical model. The model includes the calculation of the surface potential, electric field, threshold voltage, and drain-induced barrier lowering. A model for the drain current, transconductance, drain conductance, and voltage gain is also discussed. It is seen that SCEs in this structure are suppressed because of the perceivable step in the surface-potential profile, which screens the drain potential. We further demonstrate that the proposed DMDG structure provides a simultaneous increase in the transconductance and a decrease in the drain conductance when compared with the DG structure. The results predicted by the model are compared with those obtained by two-dimensional simulation to verify the accuracy of the proposed analytical model.

Two-dimensional analytical threshold voltage model of nanoscale fully depleted SOI MOSFET with electrically induced S/D extensions

A new analytical model for the surface potential and the threshold voltage of a silicon-on-insulator (SOI) MOSFET with electrically induced shallow source/drain (S/D) junctions is presented to investigate the short-channel effects (SCEs). Dividing the SOI MOSFETs silicon thin film into three zones, the surface potential is obtained by solving the two-dimensional Poissons equation. Our model includes the effects of the body doping concentration, the lengths of the side and main gates and their work functions, applied drain and substrate biases, the thickness of the gate and buried oxide, and also the silicon thin film. Our model results reaffirm that the application of induced S/D extensions to the SOI MOSFET will successfully control the SCEs for channel lengths even less than 50 nm. Two-dimensional simulation results are used to verify the validity of this model, and quite good agreements are obtained for various cases.

In-Built N + Pocket p-n-p-n Tunnel Field-Effect Transistor

The source-pocket (p-n-p-n) tunnel field effect transistor (TFET) has a narrow and highly doped N+ pocket layer between the source and channel to enhance the overall performance of the conventional p-i-n TFET. However, realizing this, N+ pocket increases the fabrication complexity since either an epitaxial growth in vertical TFETs or an implantation in planar TFETs is required to create the N+ pocket. In this letter, using the charge plasma concept, we propose a technique to realize an in-built N+ pocket without the need for a separate implantation. We demonstrate using 2-D simulations that the proposed in-built N+ pocket p-n-p-n TFET exhibits a higher ION (~20 times) and a steeper subthreshold swing (25 mV/decade) as compared with the conventional p-i-n TFET. Our approach overcomes the difficulty of creating a narrow N+ pocket doping and thus makes the p-n-p-n TFET more attractive in carrying on with the scaling trend.

Controlling the Drain Side Tunneling Width to Reduce Ambipolar Current in Tunnel FETs Using Heterodielectric BOX

In this brief, we demonstrate using 2-D simulations that the use of a heterodielectric BOX (HDB) above a highly doped ground plane can control the tunneling width at the channel-drain interface and lead to a significant reduction in the ambipolar current in tunnel FETs (TFETs). The HDB consists of SiO2 under the source and the channel regions, and HfO2 under the drain region. When the thickness of the HDB is 25 nm and the ground plane is heavily doped, we show that the drain region at the channel-drain interface is effectively depleted. As a result, the tunneling width at the channel-drain interface increases leading to a complete suppression of ambipolar conduction in a TFET even when the gate voltage VGS = -0.8 V.

Junctionless Impact Ionization MOS: Proposal and Investigation

We propose a novel junctionless impact ionization MOS (JIMOS) on a p-type silicon film using charge plasma concept. This device does not have metallurgical junctions and requires no impurity doping for creating the source and drain. This makes the JIMOS combine the benefits of an impact ionization MOS (IMOS) (steep subthreshold slope) and a junctionless field-effect transistor (JLFET) (low thermal budget process). Using 2-D simulations, we show that the performance of the JIMOS is analogous to that of a corresponding IMOS in which the source and drain regions are created by impurity doping. The proposed idea can pave the way for fabricating the IMOS using a low thermal budget process similar to that of a JLFET.

Realizing Efficient Volume Depletion in SOI Junctionless FETs

In this paper, we provide a simple and effective solution to realize efficient volume depletion and therefore, significantly reduce the OFF-state leakage current of a junctionless FET (JLFET) by replacing the SiO₂ by HfO₂ in the buried oxide (BOX). Using calibrated 2-D simulations, we show that the JLFET with a high-k BOX (HB JLFET) exhibits a considerably high I_ON/I_OFF ratio of ~10⁶ even for a channel length of 20 nm. Further, we demonstrate that the use of a high-k BOX leads to a reduction in both gate capacitance C_g and gate-to-drain feedback (Miller) capacitance C_gd.

Insight into Lateral Band-to-Band-Tunneling in Nanowire Junctionless FETs

In this paper, we investigate the nature of lateral band-to-band-tunneling (L-BTBT) component of gate-induced drain leakage (GIDL) in different nanowire junctionless FET (NWJLFET) configurations for the first time. Although the NW junctionless accumulation mode (JAM) FET has a larger ON-state current compared with the NWJLFETs, we demonstrate that the L-BTBT GIDL is larger in the NWJAMFET compared with the NWJLFET. Furthermore, we explore for the first time the application of a dual-material gate (DMG) in the NWJAMFET to suppress the L-BTBT GIDL. Using calibrated 3-D simulations, we show that the OFF-state current in the DMG NWJAMFET is reduced significantly by six orders of magnitude leading to a considerable ON-state to OFF-state current ratio (I/IOFF) of ~1010. Furthermore, the DMG NWJAMFET offers: 1) an enhanced ON-state current and 2) a significantly reduced OFF-state current compared with the NWJLFETs. Furthermore, we also demonstrate that the DMG NWJAMFET exhibits a higher transconductance than the single material gate NWJAMFET in the saturation region. In addition, we also show that there is a tradeoff between the off-state current and the intrinsic delay and the cut-off frequency in the DMG NWJAMFET. Therefore, we provide the design guidelines for appropriately choosing the work functions of the dual gates and the ratio of the length of the dual gates to the total gate length.

Compact Surface Potential Model for FD SOI MOSFET Considering Substrate Depletion Region

In this paper, by solving the 1-D Poisson equation using appropriate boundary conditions, we report a closed-form surface potential solution for all the three surfaces (gate oxide-silicon film interface, silicon-film-buried oxide interface, and buried oxide-substrate interface) of fully depleted silicon-on-insulator (SOI) MOSFETs by considering the effect of substrate charge explicitly. During the model derivation, it is assumed that the silicon film is always fully depleted and the back silicon film surface is never inverted. The calculated values of the surface potentials obtained from the proposed model agree well with the iterative solution of exact Poisson equation with a maximum relative error bound of 0.3%. In the entire model, only two square roots, one exponential, and two logarithm terms are used and the continuity and differentiability of the resultant surface potential solutions are ensured making the proposed model computationally efficient.

Controlling BTBT-Induced Parasitic BJT Action in Junctionless FETs Using a Hybrid Channel

In this brief, we demonstrate for the first time that the presence of a hybrid channel, which consists of a p⁺ layer below the n⁺ active device layer in a junctionless (JL) FET, leads to a drastically reduced BTBT-induced parasitic BJT action. Using calibrated 2-D simulations, we show that the JLFET with a p⁺ layer [which we call hole sink (HS)] has a significantly low OFF-state leakage current due to an increased tunneling barrier width, an enhanced source-to-channel barrier height, and a better provision for collecting the band-to-band tunneling (BTBT) generated holes, which results in a diminished parasitic BJT action in the OFF-state. Further, the proposed HS JLFET shows an extremely high ON-state to OFF-state current (I_ON/I_OFF) ratio of ~10⁷ for a channel length of 10 nm and a significant (I_ON/I_OFF) ratio of ~10⁴ even for a channel length of 5 nm.

An Accurate Compact Analytical Model for the Drain Current of a TFET From Subthreshold to Strong Inversion

In this paper, we have developed a compact analytical model for the drain current of a silicon-on-insulator tunneling field-effect transistor. The model includes the effects of oxide thickness, body doping, drain voltage, and gate metal work function. The model calculates the drain current using a tangent line approximation method to integrate the tunneling generation rate in the source-body depletion region. The accuracy of the model is tested against 2-D numerical simulations. The model predicts the drain current accurately in both the ON state (strong inversion) as well as in the subthreshold region.