Shubham Sahay

Controlling the Drain Side Tunneling Width to Reduce Ambipolar Current in Tunnel FETs Using Heterodielectric BOX

In this brief, we demonstrate using 2-D simulations that the use of a heterodielectric BOX (HDB) above a highly doped ground plane can control the tunneling width at the channel-drain interface and lead to a significant reduction in the ambipolar current in tunnel FETs (TFETs). The HDB consists of SiO2 under the source and the channel regions, and HfO2 under the drain region. When the thickness of the HDB is 25 nm and the ground plane is heavily doped, we show that the drain region at the channel-drain interface is effectively depleted. As a result, the tunneling width at the channel-drain interface increases leading to a complete suppression of ambipolar conduction in a TFET even when the gate voltage VGS = -0.8 V.

Realizing Efficient Volume Depletion in SOI Junctionless FETs

In this paper, we provide a simple and effective solution to realize efficient volume depletion and therefore, significantly reduce the OFF-state leakage current of a junctionless FET (JLFET) by replacing the SiO₂ by HfO₂ in the buried oxide (BOX). Using calibrated 2-D simulations, we show that the JLFET with a high-k BOX (HB JLFET) exhibits a considerably high I_ON/I_OFF ratio of ~10⁶ even for a channel length of 20 nm. Further, we demonstrate that the use of a high-k BOX leads to a reduction in both gate capacitance C_g and gate-to-drain feedback (Miller) capacitance C_gd.

Insight into Lateral Band-to-Band-Tunneling in Nanowire Junctionless FETs

In this paper, we investigate the nature of lateral band-to-band-tunneling (L-BTBT) component of gate-induced drain leakage (GIDL) in different nanowire junctionless FET (NWJLFET) configurations for the first time. Although the NW junctionless accumulation mode (JAM) FET has a larger ON-state current compared with the NWJLFETs, we demonstrate that the L-BTBT GIDL is larger in the NWJAMFET compared with the NWJLFET. Furthermore, we explore for the first time the application of a dual-material gate (DMG) in the NWJAMFET to suppress the L-BTBT GIDL. Using calibrated 3-D simulations, we show that the OFF-state current in the DMG NWJAMFET is reduced significantly by six orders of magnitude leading to a considerable ON-state to OFF-state current ratio (I/IOFF) of ~1010. Furthermore, the DMG NWJAMFET offers: 1) an enhanced ON-state current and 2) a significantly reduced OFF-state current compared with the NWJLFETs. Furthermore, we also demonstrate that the DMG NWJAMFET exhibits a higher transconductance than the single material gate NWJAMFET in the saturation region. In addition, we also show that there is a tradeoff between the off-state current and the intrinsic delay and the cut-off frequency in the DMG NWJAMFET. Therefore, we provide the design guidelines for appropriately choosing the work functions of the dual gates and the ratio of the length of the dual gates to the total gate length.

Controlling BTBT-Induced Parasitic BJT Action in Junctionless FETs Using a Hybrid Channel

In this brief, we demonstrate for the first time that the presence of a hybrid channel, which consists of a p⁺ layer below the n⁺ active device layer in a junctionless (JL) FET, leads to a drastically reduced BTBT-induced parasitic BJT action. Using calibrated 2-D simulations, we show that the JLFET with a p⁺ layer [which we call hole sink (HS)] has a significantly low OFF-state leakage current due to an increased tunneling barrier width, an enhanced source-to-channel barrier height, and a better provision for collecting the band-to-band tunneling (BTBT) generated holes, which results in a diminished parasitic BJT action in the OFF-state. Further, the proposed HS JLFET shows an extremely high ON-state to OFF-state current (I_ON/I_OFF) ratio of ~10⁷ for a channel length of 10 nm and a significant (I_ON/I_OFF) ratio of ~10⁴ even for a channel length of 5 nm.

Controlling L-BTBT and Volume Depletion in Nanowire JLFETs Using Core–Shell Architecture

In this paper, we propose the use of a p+ core in the core-shell nanowire (CS NW) architecture to significantly reduce the gate induced drain leakage and therefore, increase the ON-state to OFF-state current ratio (ION/IOFF) in n-NW junctionless FETs (NWJLFETs). We show that the lateral bandto-band tunneling induced parasitic bipolar junction transistor action is diminished in the CSJLFET due to an enhanced tunneling width and a higher source to channel barrier height. Further, we also demonstrate that the p+ core helps to realize efficient volume depletion in NWJLFETs with large NW width. Using calibrated 3-D simulations, we show that the CSJLFET exhibits a significantly high ON-state to OFF-state current ratio (ION/IOFF) of ~107 even for a channel length of 7 nm.

A Novel Gate-Stack-Engineered Nanowire FET for Scaling to the Sub-10-nm Regime

In this paper, we propose a novel dual-metal gate-stack (DMSG) architecture with HfO2 spacer for scaling the nanowire FETs (NWFETs) to the sub-10-nm regime. We demonstrate that the electric field at the channel-drain extension interface is reduced when the inbuilt electric field arising due to a difference in the work function at the interface of the two metals in the DMSG is coupled to the nanowire through the fringing fields through the HfO2 spacer. The reduction in the electric field leads to a larger tunneling width, and therefore suppresses the lateral band-to-band-tunneling component of the gate-induced drain leakage in the DMSG NWFETs. Although the gate capacitance increases in the DMSG NWFETs due to the fringing fields, this paper demonstrates that the increase in the intrinsic delay (~1.5 times) is not very significant to degrade the circuit performance drastically. Using calibrated 3-D simulations, we show that the off-state current is reduced by more than five orders of magnitude in the DMSG NWFETs, leading to a significantly high on-state to off-state current ratio of ~106 even when the channel length is scaled to 7 nm.

Symmetric Operation in an Extended Back Gate JLFET for Scaling to the 5-nm Regime Considering Quantum Confinement Effects

In this paper, we propose a double gate junctionless FET (DGJLFET) with an extended back gate (EBG) architecture for significantly improved performance in the sub-10-nm regime. Even for a channel length of 5 nm, we show using calibrated 2-D simulations that the EBG DGJLFET, when compared with the DGJLFET, exhibits: 1) an improved subthreshold swing; 2) a significantly low off-state leakage current; and 3) a considerably high ION/IOFF ratio of ~108. Furthermore, we demonstrate, for the first time, that the quantum confinement-induced bandgap widening diminishes the parasitic bipolar junction transistor (BJT) action and, therefore, facilitates the scaling of the conventional DGJLFETs to the sub-5-nm channel regime where the quantization effects are significant. Moreover, we also show, for the first time, that the DG junctionless accumulation mode FET suffers from an enhanced parasitic BJT action and, therefore, a significantly high off-state leakage current compared with the DGJLFET. In addition, we demonstrate that the loss of gate control for negative gate voltages in the DGJLFETs with larger silicon film doping (ND ≥ 2 × 1019 cm-3) is due to a shielding effect initiated by the band-to-band tunneling.

Diameter Dependence of Leakage Current in Nanowire Junctionless Field Effect Transistors

In this paper, we give a physical insight into the diameter-dependent dominant leakage mechanisms in the nanowire junctionless (NWJL) FETs. Using calibrated 3-D simulations, we show that the off-state current in the NWJLFETs with nanowire diameter less than 10 nm is governed by the drain-induced barrier lowering and the consequent source-to-channel barrier height and barrier thinning, which controls the lateral band-to-band tunneling (L-BTBT)-induced parasitic bipolar junction transistor (BJT) action. Furthermore, the quantum confinement-induced bandgap enhancement is shown to lower the probability of L-BTBT, and hence acts as the dominant mechanism in reducing the off-state current of the NWJLFETs with sub-7 nm diameter. In addition, the hole accumulation due to L-BTBT induces a shielding effect, which results in an inefficient volume depletion, leading to a large off-state current in NWJLFETs with nanowire diameters >15 nm. Furthermore, the impact of gate sidewall spacer on the L-BTBT-induced parasitic BJT in NWJLFETs has also been investigated.

Nanotube Junctionless FET: Proposal, Design, and Investigation

In this paper, we propose a nanotube (NT) JLFET for significantly improved performance in the sub-10-nm regime. We show that the tunneling width at the channel-drain interface and the source-to-channel barrier height are considerably increased in the NT JLFET due to the presence of the core gate. Therefore, the lateral band-to-band-tunneling-induced parasitic bipolar junction transistor action is diminished in the off-state of NT JLFET, leading to a significantly high on-state to off-state current ratio of ~107 even for a channel length of 7 nm. Furthermore, we demonstrate that the spacer length and dielectric constant and the core gate diameter can be used as design parameters to further improve the performance of the NT JLFETs. Therefore, we also provide the necessary design guidelines for NT JLFETs.

Hybrid CMOS-OxRAM RNG circuits

Compact, low-power random number generators (RNG) are essential for applications such as stochastic, bio-inspired-computing and secure system data encryption/communication. We demonstrate for the first time highly scalable RNG circuits based on the reset-state transient current fluctuation of resistive switching OxRAM devices. We propose- (i) single OxRAM based pseudo-random number generator (PRNG) and (ii) 2-OxRAM based true-random number generator (TRNG) circuits. The proposed hybrid RNG circuits have been validated for 10 nm thick HfOx devices at 180 nm CMOS node. Chi-square test, serial spectral test and covariance/correlation-based analysis are performed to analyze the performance of the proposed hybrid RNG nanocircuits.