Mamoru Sakugawa

Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications

A heterogeneous multicore system-on-chip (SoC) has been developed for high-definition (HD) multimedia applications that require secure DRM (digital rights management). The SoC integrates three types of processors: two specific-purpose accelerators for cipher and high-resolution video decoding; one general-purpose accelerator (MX); and three CPUs. This is how our SoC achieves high performance and low power consumption with hardware customized for video processing applications that process a large amount of data. To achieve secure data control, hardware memory management and software system virtualization are adopted. The security of the system is the result of the cooperation between the hardware and software on the system. Furthermore, a highly tamper-resistant system is provided on our SiP (System in a package), through DDR2 SDRAMs and a flash memory that contain confidential information in one package. This secure multimedia processor provides a solution to protect contents and to safely deliver secure sensitive information when processing billing transactions that involve digital content delivery. The SoC was implemented in a 90 nm generic CMOS technology.

Design of a Multi-Core SoC with Configurable Heterogeneous 9 CPUs and 2 Matrix Processors

A multi-core SoC for multi-application (recognition, inference, measurement, control, and security) is developed. The configurable heterogeneous architecture with 9 CPUs and 2 matrix processors reduced 45% power consumption. The performance-oriented multi-bank matrix processor with 2-read-1-write calculation and background I/O operation is adopted. The 1 GHz CPU is realized by the delay management network applied for any kinds of applications and process technologies.

Heterogeneous multicore SoC for secure multimedia applications

A heterogeneous multicore SoC (System on a Chip) has been developed for HD (high-definition) multimedia applications that require secure DRM (digital rights management). The SoC integrates three types of processors: two specific-purpose accelerators for a cipher and a high-resolution video decoding; one general-purpose accelerator (MX: Matrix processor); and three CPUs. This is how our SoC achieves high performance and low power consumption with hardware customized for video processing applications that process a large amount of data. To achieve secure data control, hardware memory management and software system virtualization are adopted. The security of the system is the result of the cooperation between the hardware and software on the system. Furthermore, a highly tamper-resistant system is provided on our SiP (system in a package), through DDR memories and Flash ROM that contain confidential information in one package. This secure multimedia processor provides a solution to protect contents and to safely deliver secure sensitive information when processing billing transactions that involve digital content delivery. The SoC was implemented in the 90 nm generic CMOS technology.

System performance and energy consumption improvement methodology by delay adjustable synchronizer

We propose a novel synchronizer and design methodology which control the probability of metastability quantitatively by a tunable delay and relax the data rate constraint due to the conventional synchronizer. They improve system performance and reduce energy consumption. We applied our synchronizer and methodology for two types of designs, a digital signal processor and a microprocessor. The former design consists on a unidirectional data flow by the asynchronous interface. Our methodology improves system performance by 43% and reduces total energy consumption by 37%. The latter design consists on CPU core whose frequency is fixed, and the system performance depends on the operating speed of the core. Even such a design, our methodology reduces total energy consumption by 9% keeping the same system performance. In addition, both designs have no area penalty.