Mamoru Sasaki

Fuzzy multiple-input maximum and minimum circuits in current mode and their analyses using bounded-difference equations

Multiple-input maximum and minimum circuits in current mode are proposed. The operation of these circuits is formulated using simultaneous bounded-difference equations. The exact analyses are performed by solving the bounded-difference equations. The accuracy of these circuits is better than the accuracy of binary tree realizations using two-input max/min circuits because no accumulation of errors occurs; furthermore, the operation speed is higher than the speed of the binary tree realization. The proposed circuits consist of only MOS transistors and are compatible with standard MOS fabrication processes. These circuits are useful building blocks for a real-time fuzzy controller and a fuzzy computer. >

Current-mode analog fuzzy hardware with voltage input interface and normalization locked loop

A voltage-input current-output membership function circuit (MFC) and a normalization locked loop (NLL) are proposed. They are useful building blocks for current-mode analog fuzzy hardware. The voltage-input current-output MFC consists of two-source-coupled-type operational transconductance amplifiers (OTAs). The MFC is used in the input parts of the analog fuzzy hardware system. The fuzzy hardware system can execute the singleton fuzzy control algorithm. In the algorithm, the weighted average operation is processed. When the weighted average operation is directly realized by analog circuits, a divider must be implemented. The NLL circuit, which can process the weighted average operation without the divider, is implemented using a one-source-coupled OTA. The proposed circuits were designed by using 2- mu m CMOS design rules and their operations were confirmed using SPICE simulations.<<ETX>>

7.5 MFLIPS fuzzy microprocessor using SIMD and logic-in-memory structure

Two fuzzy microprocessors have been developed as VLSI chips. One is an if-part processor with single instruction, multiple data (SIMD) architecture, and the other is a then-part processor with logic-in-memory. The system configuration using the chips can execute fuzzy inference for if-then fuzzy rules. The speed of inference including defuzzification is 7.5 M fuzzy logical inferences per second (FLIPS), and the system can process 960 rules and 16 input and output variables. The rule format can be easily changed by rewriting the instructions stored in the memory. The processors require no external memory since the knowledge-base can be stored in the internal memory.<<ETX>>

A fuzzy logic function generator (FLUG) implemented with current mode CMOS circuits

A fuzzy logic function generator (FLUG) based on the singleton fuzzy control algorithm is proposed. The normalizing operation can be removed from the original algorithm by introducing a new t-norm operation. The FLUG can be simply implemented with the current mode CMOS circuits, because the dividers are not needed. Further, to solve the problem in the current mode with respect to the restriction of the fan-out number, voltage-input, and current-output membership function circuits are constituted of operational transconductance amplifiers (OTAs), and they are used in the input parts of the FLUG. Due to the simple circuitry, the FLUG can be applied to a basic cell for the analog application-specific ICs.<<ETX>>

Realization of low sensitivity in the Hopfield model for optimal‐solution search

The mutually coupled Hopfield model can determine the local minimum of the energy function in a short time by the steepest descent of the energy function surface [1]. To use its high speed, analog implementation of the Hopfield model by an analog circuit is considered. On the other hand, no thorough study of various problems in the analog circuit, such as the sensitivity of the parameters to deviations of the element values, has been presented. From this viewpoint, this paper attempts a sensitivity analysis of the Hopfield model for the circuit parameters when the model is implemented on an analog circuit. Sensitivity analysis means in this paper a procedure in which error is provided by a normal random variable to a parameter that may be affected by the circuit implementation, and the effect on the solution is examined. It is seen that the Hopfield model is highly sensitive to error. In other words, the realization of low sensitivity is very important in implementing the Hopfield model as an analog circuit. This paper proposes a method where the diagonal element of the coupling weight matrix is set to a nonzero value and reports that the sensitivity to error can be reduced by this approach. The property is verified by a numerical simulation for the traveling salesman problem (TSP).

Introducing a parallel transit evaluation method into the sequential Boltzmann machine

In order to improve the efficiency of the Boltzmann machine processor proposed previously [13] we introduced the parallel transition evaluation algorithm. First, we analyzed convergence of the proposed parallel transition evaluation algorithm and proved mathematically convergence to a Boltzmann distribution similar to the case of the sequential Boltzmann machine. Compared with the transition probability of the previously proposed Boltzmann machine processor [13], it was theoretically clear that the efficiency was improved by the introduction of the parallel transition evaluation algorithm. Moreover, these facts were confirmed through experimental simulations. The analytical quality of the results of these simulations were identical to those of the sequential Boltzmann machine, but we were able to show that the efficiency was improved four fold. Finally, with the design of a dedicated processor, we confirmed that the amount of additional hardware for achieving the parallel transition evaluation is very small in proportion to the total number of gates (relative increment).

Implementation of a parallel algorithm in Boltzmann machine

This paper describes a implementation of a parallel algorithm in the Boltzmann Machine (BM). The implementation is the network of the two layers of managementers and the multiple groups of neurons. The features of the network are large scale parallel processing using a number of the simple single bit ALUs and effective expansion realized by multiple chips connected simple bus lines.<<ETX>>

An approach to a sequential-like parallel algorithm in a Boltzmann machine

The efficient implementation of the neural network is a key task in looking for a high speed algorithm. In this paper, we address the problem of optimizing sequential and parallel algorithms for the Boltzmann Machine (BM). We present a novel parallel algorithm similar to the sequential one in the operational results and suitable for parallel hardware implementation of a BM. Since the algorithm performance depends on the probability of the accepted state transition in the annealing process, we increase the the rate of the state change to enhance this probability. In addition, we give the mathematical function describing the rate of the state change, provide experimental data on a well-known optimization problem TSP to have a verification of the function and show that the proposed algorithm obtains much more speedup in comparison with the traditional algorithm.<<ETX>>

Bi-CMOS current mode circuits with 1 V supply voltage and their application to ADC

The authors present Bi-CMOS current mode circuits with 1-V supply voltage. The circuits are composed of current mirrors, current comparators, and current sources. The circuits have advantages such as high accuracy, high speed, high density, and low supply voltage. As an application of the circuits, an analog-to-digital converter (ADC) is presented. The ADC operates with small chip area and low power dissipation. Circuit simulations of the proposed circuits were performed using the SPICE2 program. From the SPICE simulation, 6-b resolution, 1-V supply voltage, 5-MHz sampling rate, and 1.0-mW power dissipation were confirmed.<<ETX>>

A composition of the neural network using switched-capacitor circuit

A switched-capacitor (SC) neural network is described. The motion of the SC neural network is represented with stochastic difference equations. The network consists of two-state neurons (ON-OFF neurons). The equations can lead to a convergence to global minima even with the two-state neurons by introducing the technique of simulated annealing. The two-state neurons make the circuits of the activation function and multiplication very simple. The network limitation of the SC neural network is analyzed in detail, and the circuit performance of 32.8 GCPS is confirmed. The computational capacity of the SC neural network is confirmed in connection with the solution of an optimization problem.<<ETX>>