Hirokuni Fujiyama

A 0.13um CMOS ultra-compact DVD SoC employing a full digital equalizing PRML read channel

A 0.13 /spl mu/m CMOS DVD SoC has been developed, reducing the die size from a previous 64 mm/sup 2/ to 34mm/sup 2/ without degrading its performance and functionality, by optimizing the chip architecture and implementation scheme in the same generation process technology. The presented SoC features a novel PRML read channel, employing full digital equalizers with an oversampling method to improve system stability while keeping channel quality.

A 200 MHz 7th-order equiripple continuous-time filter by design of nonlinearity suppression in 0.25 /spl mu/m CMOS process

7th order equiripple filter with cutoff frequency of 200 MHz is developed in a 0.25 /spl mu/m CMOS process. A new design method has been adopted to obtain enough accuracy and linearity in high frequency operation. Optimal device sizes are determined that maximize the accuracy. The most suitable filter configuration is determined that suppresses the nonlinearity of the transconductors. Experimental results satisfy group delay variation of /spl plusmn/5% and THD of less than 1% for a 400 mVpp differential input.