Yuji Shirai

High-performance vertical interconnection for high-density 3D chip stacking package

The three-dimensional (3D) chip stacking technology developed in ASET is a leading technology for realization of a high-density and high-performance system-in-package (SIP). As for the advanced interconnection technology, a 20-/spl mu/m-pitch low impedance vertical interconnection through Cu through via (TV) within thin chips plays the following roles: wide signal bus and very short electrical path for high-frequency signal transmission, strong power supplies and stable ground lines. The vertical interconnection was fabricated by inter chip connection (ICC) process, which includes Cu bump bonding (CBB) utilizing Cu-Sn diffusion for connecting Cu TVs without the formation of bumps on the chip back surface and encapsulation micro thin gap between chips. We elucidate the Cu-Sn diffusion phenomena and Cu oxide influence which were important CBB issues to realize the minute interconnection of Cu TVs. The temperature cycling test (TCT) was performed on chip on chip (COC) and 3D chip stacking structures fabricated by ICC process, and over 1,000 cycles reliability was confirmed. The consistent fabrication of vertical interconnection was realized. Then, we conducted the two important electrical evaluations. One is the DC resistance of the vertical interconnection, which measured only 15.4 m/spl Omega/ per layer. Another was the signal transmission delay, and only 0.9 ps was confirmed. Therefore, the vertical interconnection with Cu TV and ICC demonstrates the excellent capability of high performance interconnections on 3D chip stacking package. In addition, the micro scale strip line was evaluated to realize advanced SIP. The eye diagram on 3 Gbps indicated sufficient transmission. We will be able to realize high performance advanced SIP utilizing the vertical interconnection and high-speed horizontal line.

A New Silicone Gel Sealing Mechanism for High Reliability Encapsulation

Plastic molded packages for large-scale integrated (LSI) devices are widely utilized for low-cost computer equipment. The environmental reliability of conventional plastic molded packages, however, is inferior to the reliability of hermetically sealed ceramic packages. A sealing mechanism for the chip, using a silicone jelly as an encapsulation, is discussed.

A CPU chip-on-board module

A CPU chip-on-board module for low and midrange computers is described. The module consists of a CPU bare chip, 24 SRAMs packaged in SOJ packages, and some decoupling capacitors. The module substrate is a printed circuit board (PCB) made of bismaleimide-triazine resin. The module (156 mm/spl times/58 mm) consists of four signal metal layers and four power/ground metal layers. A square clearance hole (17 mm/spl times/17 mm) for the CPU is formed in the central part of the PCB. A thermal spreading metal is glued to the PCB from the rear side, covering the square hole, and the CPU chip is die-bonded onto the metal plate. The thermal resistance can be made smaller than 2/spl deg/C/W with 0.4 m/s of wind velocity. Numerical analysis of electrical characteristics of the module shows that it can reduce signal delay time from the CPU to cache memories by 10% compared with that of a daughter board type module with the CPU packaged in a pin-grid array package. It is estimated that simultaneously switched noise can be reduced by 60% from that of the daughter board type module. >

Development of a 1000-pin fine-pitch BGA for high performance LSI

A 1000-pin fine-pitch BGA has been developed by using a 50-/spl mu/m ultra fine pitch wire bonding technique. This package can be mounted with a chip with dimensions ranging from 14 mm/spl times/14 mm to 16 mm/spl times/16 mm. This package also has signal lines that have an embedded microstrip line structure. Also it has a package size heat spreader, which means that the electrical characteristics are such that the package can be applied to an LSI operating at a frequency of about 800 MHz. The thermal characteristics are such that the package can be applied to 10 W devices without the need for a fin. Furthermore, this BGA package has been confirmed to be sufficiently reliable.